TM4C1294NCPDT Debugging/Programming Interface Standard?

Hello Thomas

The following wiki resource will be useful

processors.wiki.ti.com/.../JTAG_Connectors

Regards
Amit

Also this from ARM

infocenter.arm.com/.../cortex_debug_connectors.pdf

I do recommend the small 10 pin connector.

Robert

May I second that small (0.050" pitch) header/receptacle.

While you've limited your issue to the JTAG connector - the use of a (proper) JTAG probe often saves time/funds/misspent effort. Poster Robert and my small group swear by and (only) use "J-Link" from Segger.

Should you go that route this (forum) vendor produces/sells a very nice 20 pin to 10 pin (mini) adapter. (ADA2-A or such)

Thank you for your suggestions.  I am a hardware engineer who is desperately trying to complete the product schematics, and dealing with a balky firmware engineer who keeps changing his mind on the tools.  At this point, I have decided to implement multiple debug connectors - the Cortex 10-pin (50-mil), TI 14-pin (100-mil), and possibly the TI 20-pin (2.00mm).  I have figured out most of the signal connections, but have a few remaining that need definition, and I am hoping someone here can fill in my blanks for what to do with TDIS, TRCK, EMU0 & EMU1, and EXT_DBG.  Also, there is nRST and nTRST - I assume these are reset signals, but how do they differ?

Thanks again for your kind assistance.  It surely would be good if TI produced an app note for the TM4C1294NCPDT that described the debug connection and tool choices.

Hello Thomas,

Multiple options for debug header is fine, but would increase the BOM Cost on every PCB. I would suggest using only 1 Header and an adapter board with header options. This way you can have the 100s of main PCB and a couple of adapter PCB w/o having to

(a) Increase Cost
(b) Work in an undecided Tool Option.

An Application Note is indeed planned for Apr-May Time Frame on the Debug Connection and Tool Choices.

Regards
Amit

Hello Amit,

This is a pilot run (~100 units), and we will stuff only the connector required. The only added cost will be the fabrication of the drilled holes for all of the connector options, which is negligible. We may make a handful of boards with all connector options stuffed. After the pilot run is complete, we will likely revise the PCB, at which point we will have surely settled on an appropriate connector.

I am still looking for information on the signals that I mentioned above - can you shed any light on this? Thank you!

Hello Thomas,

TDIS: Must be connected to GND on the PCB
TRCK: Kept Open as TM4C devices do not support Return TCK
EMU0 - EMU1: No Connect
nRST must be connected to the Pad Reset pin of the TM4C
nTRST: No Connect
EXT_DBG: Which pin is this and on which JTAG header did you see the same?

It is still additional PCB area, and if there is a problem on the final board, it will be extremely helpful to have the adapter board handy...

Regards
Amit

I would suggest against the 14 pin connector. It's non-standard and not very widespread. Likewise the 20 pin is particular to TI. If you are going to use a 20pin then the only obvious choice is the standard 20 pin JTAG connector.

There are inexpensive adapters for the standard 20pin to standard 10pin connection. I suspect TI has adapters from their proprietary connectors and if not they would be easy to make.

Or you could just tell the firmware engineer to use standard tools :)

Robert

Hello Amit,

The EXT_DBG signal is found in the schematic for the DK-TM4C129X (www.ti.com/.../spmu360.pdf) on p.35. It connects to pin 5 of J1.

LOL. "Tell" the firmware engineer to use standard tools. He was ready to build the debugger out of a TM4C1294XL development board . . .

Hello Thomas

The EXT_DBG pin on the DK-TM4C129X is not required on a standard debug pod. the pin is used by the on board ICDI to detect if an external debugger is connected, so that the on board ICDI can tristate the JTAG pins and allow the external debug pod to drive them

Regards
Amit

NIH run amok, that'll cost more than a high quality commercial tool.

Robert

Or as the old proverb goes, penny wise and pound foolish

Is it not true that (most) productive firmware engineers have keen awareness of JTAG probes and the necessary interconnects?

Deviation from (known) solid toolsets makes no sense.

Often those (unfamiliar) w/JTAG neglect the installation of pull-up Rs @ each/every JTAG pin - instead relying upon "internal, MCU ones." And then - very often - their programming & debug is plagued w/issues - caused by the slewed signal rise/fall times inherent w/the "excessive resistance" offered by the internal pull-ups. Time & again my small firm has gassed up the twin - flown to clients - added external pull-ups - and restored (or) achieved initial communications.

Working (sometimes) under (idealized) conditions - may not prove, "Good enough." Risk-Reward clearly cries out for external pull-up Rs...

"but nothing that conclusively and succinctly ties it together.  Can someone kindly provide (or point me to a location where I can find) the complete and exact documentation describing a debug/program connector?"

Unfortunately this is sometimes too common. For the type of connector you've got some recommendations. For the actual mechanics of it try this:

Look at the TM4C1294NCPDT connected launchpad manual here:

http://www.ti.com/lit/ug/spmu365b/spmu365b.pdf

Page 36 shows you the 1294. The schematics are a mess, but fortunately the document is text searchable, which makes it easier to find what is connected to what by searching on signal names. A JTAG/debug connector in a new design would be like this but with the 0R links removed (page 41 bottom left) to separate the TM4C123 based ICDI portion of the board, and the probe going into the target side of the X1 connector. And note the JTAG pullups. What I can say is that the connection in this form is very stable. The ICDI based connection much less so.

As Amit says the EXT_DBG line isn't needed to JTAG the 1294. All that signal does, when shorted to GND is cause the TM4C123 ICDI device to tristate its lines and gets it 'out of the way' for the external JTAG probe to be connected. Removing all the OR link resistors does the same job but more permanently.

Don't forget your target's voltage rail for sensing too, if the probe needs it.

Hello Pete,

There is no single document on JTAG but a mix of documents and wiki links. This is changing as we are consolidating JTAG as an application note.

Regards
Amit

Hi Amit,
That no single document is very apparent. I look forwards to the consolidated document for the sake of new users. Also the ability for forum members to feedback into any modifications to it would be valuable I feel. There's much experience here.

Hello Pete,

cb1 started the thread

e2e.ti.com/.../423619

I use this as my go-to post for checking I am taking all the feedback. You may contribute to the same.

Regards
Amit

Thankyou for that Amit, very interesting. I shall have a read. Not sure how much I can contribute at the C level, as you know I'm happier in assembler. So most of my contributions have been at datasheet level and these have been sent direct to Bogdan Nicola at TI, who sent them on to the relevent team. However having recently been looking at TI's driverlib for the USB host I may have some stuff for you. I'll round it up and post it to the thread you linked to.

Hello Pete

That's Great. Please use the singular forum post for all code/idea/comments/critical inputs.

Regards
Amit

Amit Ashara said:

Hello Thomas,

Multiple options for debug header is fine, but would increase the BOM Cost on every PCB. I would suggest using only 1 Header and an adapter board with header options. This way you can have the 100s of main PCB and a couple of adapter PCB w/o having to

(a) Increase Cost
(b) Work in an undecided Tool Option.

An Application Note is indeed planned for Apr-May Time Frame on the Debug Connection and Tool Choices.

Regards
Amit