EMIF Time Gap between consecutive Read/Write Operation

Hi TI Experts,

I have a question about Hercules EMIF Timing.

I'm using TMS570LS1114ZWT interfacing a FPGA through EMIF. When MCU access the FPGA, I noticed on the bus there is more than 20 clocks time gap between two consecutive read/write. I would like to know if this time gap can be reduced? I need faster read/write for this FPGA.

The settings of Halcogen is as follows.