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Simultaneous adc with external trigger + DMA

PAk
Mastermind 7015 points

Hello.

In our project, until now, the sampling of two ADC channels was made via only one ADC (ADC0). Due to phase requirements, I need to sample those channels simultaneously, via ADC0 and ADC1.

The ADC0 was triggered via an external pin at 500khz, and the data was captured via PING-PONG buffer with the DMA and it was working fine.

As I understand, now I need to set up another sequencer for the ADC1, another DMA channel for the ADC1, and I need to change my DMA setup on the ADC0 because I will be capturing only one channel (half the data). Right?

Does the ARB size change as well?

Will I get two interrupts instead of only one? If so, will those interrupts be consecutive at nearly the same time? 

Do you have an example for this?

Thank you

PS: Besides I have seen that there is a bug with ADCSequenceConfigure and ADC1 in Tivaware. What workaround do you recommend?

  • 0
    TI__Guru**** 244400 points
    Hello PAk

    No. The ARB size does not need to change. Each ADC and each sequencer has its own DMA request and interrupt mechanism. You would see two interrupts for the 2 ADC's being used. If the Phase is enabled then the interrupts shall be separate by the approximately the Phase delay at the shortest point of execution.

    As for the bug described, the fix is to remove the ADC1_BASE with ui32Based and recompile the driverlib and use the new driverlib.lin during the linker phase of the project.
  • 0 in reply to Amit Ashara
    Mastermind 7015 points
    The idea is to trigger both ADC at the same time (0 phase), since the trigger is an GPIO pin (external trigger), is it necessary to set the phase parameter?
    Is there a way to configure which interrupt will arrive first?
  • 0 in reply to PAk
    TI__Guru**** 244400 points
    Hello PAk

    No, the interrupt generation is based on the conversion complete. The setting of Phase would allow control on the sampling by a single ADC and then its propagation. Without setting the phase the sampling of the trigger would be handled by the ADC's themselves independently which may result in change of the interrupt generation.
  • 0 in reply to Amit Ashara
    Mastermind 7015 points
    Then....how could we assure that both ADCs are sampling at the same time with the same external clock?

    Regards
  • 0 in reply to PAk
    Guru 47900 points

    Re: Identical sampling time (aperture) across multiple ADC Channels.

    Might this be best served by TWO (or more) external ADCs - clocked in unison - via a common clock?
    MCU as, "kitchen sink" may not always prove (best) "cat-skinning technique."    Specialized devices DO exist for good reason...

    At the very least - your acquisition & build of this suggested (external) circuit would well, "inform" you of the MCU's capability (by enabling comparison of the MCU's results vs. those of (more proper) external devices) - that's important - is it not?

    In addition - you may find multiple resolution (external) ADCs - which all accommodate the SAME pcb footprint & signal inventory.    (the ability to "tailor" both the ADC's speed of conversion as well as its conversion depth is sure to prove of value - at some point w/in your design effort...)

  • 0 in reply to PAk
    TI__Guru**** 244400 points
    Hello PAk

    You mean external trigger?

    One way is to monitor the ADC analog channel with a Pull Up resistor. When the ADC sampling is started, there is a small dip in the voltage. By putting two scope probes it can be checked if the dips on the two channel happen at the same time. A persistence capture will show the variation if any on the sampling of the channels.
  • 0 in reply to Amit Ashara
    Guru 47900 points
    Hi Amit,

    You provide great "MCU specific insight" w/that suggestion. (i.e. pull-up R tied to each ADC channel - we must try that on (other's) MCUs)

    That said - should poster drive BOTH ADC Channel inputs w/the SAME, Time-Variant, analog signal - the degree of "match" will provide insight...
    (I'm thinking of fast rising, linear ramp employed as (common) input signal to both ADC Channels...)
  • 0 in reply to cb1
    Mastermind 7015 points

    cb1 said:
    Might this be best served by TWO (or more) external ADCs - clocked in unison - via a common clock?
    MCU as, "kitchen sink" may not always prove (best) "cat-skinning technique."    Specialized devices DO exist for good reason...

    Yes, but this is a test of a proof of concept on an already made board. Everything is routed, in the end product we will probably use a dedicated DSP....but it is better to make the test as close as possible to the final signal.

    Amit Ashara said:
    Hello PAk

    You mean external trigger? 

    One way is to monitor the ADC analog channel with a Pull Up resistor. When the ADC sampling is started, there is a small dip in the voltage. By putting two scope probes it can be checked if the dips on the two channel happen at the same time. A persistence capture will show the variation if any on the sampling of the channels.

    I was asking about how to setup the ADCs/DMAs modules in sw to make them sample at the same time via an external pin. 

    To test the phase, I think it is better to inject a sin signal in both channels, and calculate the phase of the FFT or the ddelay between them.

  • 0 in reply to PAk
    TI__Guru**** 244400 points
    Hello PAk,

    Simplify. You are complicating a situation by running FFT to figure out the delay (which by the way works on quantization on the number of samples and the frequency range of response.)
  • 0 in reply to Amit Ashara
    Mastermind 7015 points

    I was stating the same as the partner ....a linear ramp would also do it:

    Inject a known signal, and measure the difference between the sampled points of  both ADCs. If everything is good, they have to be almost the same (of course, you could do that using FFTs if your sampled signal is inside Nyquist)....so let's keep it simple....Linear ramp.

    The ADC clock is received in an GPIO pin, and selected via: GPIOADCTriggerEnable(GPIO_PORTM_BASE, GPIO_PIN_7);

    Would it work for both ADCs?

    How should we set up the rest of the ADCs and DMA blocks to get simultaneous sampling of two channels?

  • 0 in reply to PAk
    Guru 47900 points

    PAk said:
    this is a test of a proof of concept on an already made board.

    Perhaps much depends upon the, "Degree of Proof" desired.   Firm/I are "never impressed" never satisfied with, "Restrictions imposed by "already made!""

  • 0 in reply to PAk
    TI__Guru**** 244400 points
    Hello PAk,

    Yes, that would work. There is no selection of the trigger pin at the ADC. It is only external trigger. All qualified pins are OR-ed together to form the external trigger.
  • 0 in reply to Amit Ashara
    Mastermind 7015 points

    Amit Ashara said:
    Hello PAk,

    Yes, that would work. There is no selection of the trigger pin at the ADC. It is only external trigger. All qualified pins are OR-ed together to form the external trigger.

    Ok, but will both ADC then sample at the same time? 

    Is it necessary to set the phase?

  • 0 in reply to PAk
    TI__Guru**** 244400 points
    Hello PAk

    That is not guaranteed as I mentioned earlier. When NOT using phase the trigger sources are independently synchronized by each of the ADC's at the ADC clock of 32MHz (corresponding to 2MSPS). There MAY be one clock edge difference.
  • 0 in reply to Amit Ashara
    Mastermind 7015 points

    Amit Ashara said:
    Hello PAk

    No, the interrupt generation is based on the conversion complete. The setting of Phase would allow control on the sampling by a single ADC and then its propagation. Without setting the phase the sampling of the trigger would be handled by the ADC's themselves independently which may result in change of the interrupt generation.

    Ok, I tried setting both ADCs with DMA on an external trigger, and there is not any delay on the samples.

    In fact, if I use the same input for both of them, the samles are virtually identic!! No delay, even one clock.

    Thank you for everything.

  • 0 in reply to PAk
    TI__Guru**** 244400 points
    Hello PAk,

    As cb1 has stated in quite some posts, you are relying on a single device to generalize that there will not be a delay. The position of the external trigger viz-a-viz every device timing may leave the statement "not TRUE".
  • 0 in reply to Amit Ashara
    Mastermind 7015 points
    Tried it in 3 different devices....lauchpad included.
    How many to generalize?
  • 0 in reply to PAk
    TI__Guru**** 244400 points
    Hello PAk,

    What about the position of the External trigger w.r.t to the ADC clock. Since the ADC clock is not directly visible outside, a synchronous sweep with a psuedo-end of conversion signal would do the trick.
  • 0 in reply to Amit Ashara
    Mastermind 7015 points

    Amit Ashara said:
    position of the External trigger w.r.t to the ADC clock. Since the ADC clock is not directly visible outside, a synchronous sweep with a psuedo-end of conversion signal would do the trick.

    That is exactly what i am doing...and it is working!!!

  • 0 in reply to PAk
    TI__Guru**** 244400 points
    Hello PAk

    And what is the granularity of the sweeping external trigger w.r.t the end of conversion signal? Also not all the devices you have may belong to different silicon characterized.
  • 0 in reply to Amit Ashara
    Mastermind 7015 points

    Amit Ashara said:
    And what is the granularity of the sweeping external trigger w.r.t the end of conversion signal? Also not all the devices you have may belong to different silicon characterized.

    Around 100ns....

  • 0 in reply to PAk
    TI__Guru**** 244400 points
    Hello PAk,

    That is not sufficient enough when compared to the sampling clock of 16 or 32 MHz. The movement of the external trigger must be at least 1/2 of the clock for any base check and I would normally be sweeping it in 100 ps to get to a 99% confidence. However without knowing the characterized nature of the device any data collected would only go as far 95% range in terms of always being sampled at the same time. If you are OK with 1 ADC clock error, then you are in a much better state of behavior conformity of the devices.
  • 0 in reply to Amit Ashara
    Guru 47900 points
    As a Tech Investor - there appears to be significant "rooting" for poster's "method & results."

    And - most damning - that "rooting" is coming from the (supposedly, truth-seeking) science-based developer. That's just scary - I'd pass on this development.

    Firm foundations result NOT from rooting - but instead from, "sweating the details" - and complying w/the vendor's guidelines...
  • 0 in reply to Amit Ashara
    Mastermind 7015 points

    Amit Ashara said:
    Hello PAk,

    That is not sufficient enough when compared to the sampling clock of 16 or 32 MHz. The movement of the external trigger must be at least 1/2 of the clock for any base check and I would normally be sweeping it in 100 ps to get to a 99% confidence. However without knowing the characterized nature of the device any data collected would only go as far 95% range in terms of always being sampled at the same time. If you are OK with 1 ADC clock error, then you are in a much better state of behavior conformity of the devices.

    Sorry...I meant 100ps...100ns is the granularity of the DMA interrupt.

    In fact, the ADC clock signal and EoC signal are coherent in our system (generated from the same crystal)

  • 0 in reply to PAk
    TI__Guru**** 244400 points
    Hello PAk

    I was referring to the granularity of the signal movement. 100 ns is the high period of the external trigger that you are referring to and not to the granularity of the DMA interrupt.