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TM4C129ENCPDT: Simultaneous sampling of 8 ADC channels with DMA

Josue Pareja
Expert 1605 points
Part Number: TM4C129ENCPDT

I have been sampling 8 signals from an ultrasonic array, each signal is sampled by an ADC channel at maximun sampling rate of ADC0 (125 Ksps) , the problem is that the ultrasonic signal is arriving at different times to the sensors that are equaled separate from the ultrasonic source, what I want to know is if the analog digital conversion of 8 channels is not simultaneous, I am using a timer for DMA.

Here is ADC configuration:

    ADCClockConfigSet(ADC0_BASE,ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_FULL, 1);
    ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_TIMER, 0);
    ADCSequenceStepConfigure(ADC0_BASE, 0 , 0, ADC_CTL_CH19);                             // PK3
    ADCSequenceStepConfigure(ADC0_BASE, 0 , 1, ADC_CTL_CH18);                             // PK2
    ADCSequenceStepConfigure(ADC0_BASE, 0 , 2, ADC_CTL_CH17);                             // PK1
    ADCSequenceStepConfigure(ADC0_BASE, 0 , 3, ADC_CTL_CH16);                             // PK0
    ADCSequenceStepConfigure(ADC0_BASE, 0 , 4, ADC_CTL_CH0);                              // PE3
    ADCSequenceStepConfigure(ADC0_BASE, 0 , 5, ADC_CTL_CH1);                              // PE2
    ADCSequenceStepConfigure(ADC0_BASE, 0 , 6, ADC_CTL_CH2);                              // PE1
    ADCSequenceStepConfigure(ADC0_BASE, 0 , 7, ADC_CTL_CH3 | ADC_CTL_END | ADC_CTL_IE);   // PE0
    ADCSequenceDMAEnable(ADC0_BASE, 0);

 

  • 0
    Guru 117855 points
    You are correct in "sensing" that the ADC is "unable" to perform "simultaneous" conversions.

    The neat code block you've provided signals such - through its use of "ADCSequenceStepConfigure()" with "Step" being the prime identifier of, "One at a Time" operation! I believe that your MCU has two independent ADC modules - and thus (may) be able to perform "two simultaneous channels" of conversion - but no more. (your detailed read of the MCU manual will reveal)

    Do you (really) know the penalty imposed - by the "slight" variation in time - of each analog data acquisition?
    It IS possible to run the ADC at a far faster sampling rate - is it not? That reduces the time delay between each acquisition.