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TM4C129XNCZAD: Deep Sleep Mode issue

Narendra DV
Prodigy 160 points
Part Number: TM4C129XNCZAD
Other Parts Discussed in Thread: UNIFLASH, TM4C1292NCPDT

Hi,

We have custom board with TM4C129XNCZAD microcontroller with super cap support. 

S/W: TI-RTOS, TI-ARM Compiler 5.2.5

Whenever power fails, we save the context the board to Internal EEPROM.  After this we  intend to put the micro-controller in deep sleep so that super cap discharge reduced.  We are using PK6 as GPIO pin for wakeup signal. We have 5 tasks running

The deep sleep initialization code is as below

//
// Enable Auto Clock Gating Control.
//
SysCtlPeripheralClockGating(true);

SysCtlPeripheralDeepSleepEnable(SYSCTL_PERIPH_GPIOK);

SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_ADC0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_ADC1);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_CAN0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_CAN1);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_COMP0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_EMAC0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_EPHY0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_EPI0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOD);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOE);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOF);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOH);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOJ);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_HIBERNATE);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_CCM0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_EEPROM0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_FAN0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_FAN1);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOL);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOM);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPION);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOP);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOQ);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOR);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOS);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_GPIOT);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_I2C0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_I2C1);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_I2C2);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_I2C3);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_I2C4);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_I2C5);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_I2C6);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_I2C7);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_I2C8);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_I2C9);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_LCD0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_ONEWIRE0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_PWM0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_PWM1);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_QEI0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_QEI1);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_SSI1);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_SSI2);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_SSI3);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_TIMER0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_TIMER1);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_TIMER2);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_TIMER3);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_TIMER4);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_TIMER5);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_TIMER6);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_TIMER7);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_UART0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_UART1);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_UART2);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_UART3);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_UART4);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_UART5);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_UART6);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_UART7);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_UDMA);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_USB0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_WDOG0);
SysCtlPeripheralDeepSleepDisable(SYSCTL_PERIPH_WDOG1);

//
// Set the clocking for Deep-Sleep.
// Power down the PIOSC & MOSC to save power and run from the
// internal 30kHz osc.
//
SysCtlDeepSleepClockConfigSet(63, (SYSCTL_DSLP_OSC_INT30 |
SYSCTL_DSLP_PIOSC_PD | SYSCTL_DSLP_MOSC_PD));
//
// Set SRAM to Low power when in Sleep Mode.
//
//
SysCtlDeepSleepPowerSet(SYSCTL_LDO_SLEEP|SYSCTL_TEMP_LOW_POWER|SYSCTL_FLASH_LOW_POWER|SYSCTL_SRAM_LOW_POWER);

//
// Set LDO to 0.90V in Sleep.
//
//
SysCtlLDODeepSleepSet(SYSCTL_LDO_0_90V);

We get an interrupt on power fail. The ISR posts an event. In the event after the context data has been saved.

The following code is called the microcontroller to sleep

//
// Go into Sleep Mode.
//
//SysCtlDeepSleep();

The current consumption measured across the micro-controller gets reduced from 120 mA to around 55 mA.  The data sheet says it should well below 20 mA.  Are all my initialization correct?  Do I have to do anything to reduce the current consumption. Also I saw  the micro-controller getting locked in.  Both times I had to use uniflash to unlock the microcontroller.

TIA

Narendra

  • 0
    Prodigy 160 points
    Small Correction to the post.

    //
    // Go into Sleep Mode.
    //
    SysCtlDeepSleep();
  • 0
    TI__Guru**** 244400 points
    Hello Narendra

    55 mA is too high. I have a TM4C1292NCPDT device with almost the same configuration running in the uA range. Can you make sure that the VDD supply for the device is separate from any other components on the board.

    To base line the board, run the same outside of TI RTOS scope using TivaWare alone.

    As for the issue with lock, this would happen since the system clock in deep sleep is 30KHz, while the JTAG is in MHz. The requirement for JTAG is that the TCK for JTAG needs to be not more than 1/10th of the system clock. So for the moment the unlock sequence is fine. I would always keep a GPIO via a switch at the start of the program to hang the device in a while(1) loop so that a simple reset with the switch pressed cause the device not to go to deep sleep mode and allow the debugger to connect.