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CCS/TMS570LC4357: Unable to configure the ECC for on-chip 4MB Flash and 512KB EEPROM

Sripad Kulkarni
Prodigy 60 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

Hi,

Can anyone please help me with information on configuration of ECC for on-chip RAM and FLASH for TMS570LC570 and error signaling with exception handling. After reading the datasheets, reference manual and going through some forums I could understand that not just the RAMCTRL L2RAMW Module Control Register be updated for ECC DETECT EN field with a value of 0xA, but also the "ATCM, B1TCM and B0TCM ECC check" in the CP15 Auxilary Control Register and the "Event enable" bit of the CP15 PMNC register be set. I tried with the code snippet shown below but still cant induce an ECC error. I get to understand that the on-chip RAM and FLASH is accessed on AXI-M L2 Bus interface(unlike its predecessor LC3137 which is based on the ARM Cortex R4 architecture which uses TCM interface to access RAM  & Flash and not on AXI-M L2 Bus). So if I am doing something wrong here please help me correct it.

;------------Enable ECC on RAM & FLASH --------------------------

   .def     CoreEnableRamFlashEcc
   .asmfunc

CoreEnableRamFlashEcc

 MRC p15,#0,r1,c9,c12,#0 ; Reading secondary Aux secondary Reg.
 ORR r1, r1, #0x00000010
 DMB
 MCR p15,#0,r1,c9,c12,#0 ; Enable export of the events in PMNC
 ISB ; To ensure the write before proceeding
 MRC p15, #0, r1, c1, c0, #1
 ORR r1, r1, #0x1 <<25 ; ATCM ECC Check Enable
 ORR r1, r1, #0x1 <<26 ; B0TCM ECC Check Enable
 ORR r1, r1, #0x1 <<27 ; B1TCM ECC Check Enable
 DMB
 MCR p15, #0, r1, c1, c0, #1
 ISB ; To ensure the write before proceeding
 MOV PC, lr

   .endasmfunc

;------------Disable ECC on RAM & FLASH--------------------------

      .def     CoreDisableRamFlashEcc
   .asmfunc

CoreDisableRamFlashEcc

 MRC p15, #0, r1, c1, c0, #1
 MVN R0,#0x1 <<25  ; ATCM ECC check disable
 AND R1 ,R1, R0
 MVN R0,#0x1 <<26  ; B0TCM ECC check disable
 AND R1 ,R1, R0
 MVN R0,#0x1 <<27  ; B1TCM ECC check disable
 AND R1 ,R1, R0
 DMB
 MCR p15, #0, r1, c1, c0, #1
 ISB ; To ensure the write before proceeding
 MRC p15,#0,r1,c9,c12,#1
 MVN R0,#0x00000010 ; Disable export of the events in PMNC
 AND R1 ,R1, R0
 DMB
 MCR p15,#0,r1,c9,c12,#0
 ISB ; To ensure the write before proceeding
 MOV PC, lr

   .endasmfunc

Appreciate your quick response!

Thanks & best,

Sripad Kulkarni

  • 0
    TI__Guru 59540 points
    Hello Sridap,

    In the TMS570LC43xx device ECC on SRAM and Flash is enabled by default. Are you using code generated by Halcogen? Have you had a look at the SafeTI Diagnostic Library to see how they have implemented the LC43xx ECC test of function routines? using these two development tools should help in understanding how to perform the tasks you are trying to implement.

    Also, SRAM and Flash are no longer located on the TCM interface since they are now L2 memories.
  • 0 in reply to Chuck Davenport
    Prodigy 60 points
    Hello Chuck,

    Thanks for letting me know about SafeTI Diagnostic Library. Will look there to find answers. Yes, after going through the datasheet and reference manual I did figure out that the ECC on SRAM and Flash is enabled by default and they aren't on TCM anymore, we just have to export the events in PMNC registers.

    Will get beck to you in any case to let you know on my progress.

    thanks again for your quick response,

    regards,
    Sripad Kulkarni
  • 0 in reply to Sripad Kulkarni
    Prodigy 60 points
    Hi Chuck,

    I was able to successfully test the ECC, my initial snippet of code to enable the ECC on SRAM did work fine (however, enabling TCM ECC check doesn't matter since ECC check for RAM is enabled by default), I was in fact trying to corrupt the ECC values by disabling ECC, updating the SRAM and then enabling back the ECC, this just doesn't work as I came across few discussions from other forums which says that despite of disabling the ECC check the controller still keeps updating ECC values, therefore, the correct method is update the DIAG_DATA_TESTVECTOR, ECC reg in L2RAMW Reg bank with desired test irritants and then trigger the test through RAM_TEST reg. Finally, I was able to test it and see the controller reporting the fault on ESM Group 2.3 (which by default is mapped to High Priority Interrupt and routed to VIM channel 0, an FIQ interrupt)

    However, I couldn't see the controller branching to FIQ vector 0x001C even after enabling the FIQ bit in CPSR.

    I have used to the code below to enable both FIQ and IRQ

    BT_EnableInterrupts

    CPSIE IF
    BX LR

    .endasmfunc

    May I know what am I missing here ?

    thanks & best
    Sripad Kulkarni
  • 0 in reply to Sripad Kulkarni
    Prodigy 60 points
    Correction, to the post above. A fault is reported on ESM Group 2.7 (L2RAMW - Uncorrectable error type B) and not on Group 2.3. Unable to take to FIQ vector.
  • 0 in reply to Sripad Kulkarni
    TI__Guru 59540 points

    Hello Sridap,

    My apologies for the long delay getting back with you. Can you clarify if you are using Halcogen generated code or if you are writing your own? The FIQ interrupt can be added to the sys_interrupts.asm file if it isn't already there. The associated interrupt handler is defined within Halcogen as well.

    Note that Flash and RAM ECC error handling is significantly different in the LC4357 due to the new bus structure. Generally, uncorrectable errors are routed through the EPC specifically this means the same error as noted by ESM Group2 channel 3.

    Group 2 channel 7 is a different type of error altogether from the uncorrectable error noted by ESM2.3. The ESM 2.7 Uncorrectable Error  Type B applies to the following error types:

  • 0 in reply to Chuck Davenport
    Prodigy 60 points
    Hello Chuck,

    Thank you for your patience and response on my questions. I am wrote those code on my own as I didn't find any option in HalCoGen to generate the code for ECC. Yes I agree with you. The ESM Group 2.7 Error was definitely not the uncorrectable error types. It was generated due to memory scrubbing through the DIAG_DATA_TESTVECTOR, ECC reg in L2RAMW Reg bank if I am not wrong.

    Now, I am stuck in a new problem. Since I have enabled the event export bit in The PMCR Register bit 4. I am always getting an ESM group2.3 interrupt during debugging. The same is not seen if I don't put a breakpoint and run the code till the end of the program loop. I am in need of your help very badly. Could you please suggest me on what's going wrong ?

    Thanks again,
    regards,
    Sripad Kulkarni
  • 0 in reply to Sripad Kulkarni
    TI__Guru 59540 points
    Hello Sridap,

    This is, most likely, a result of speculative fetches that are happening to areas where you don't have ECC defined. To avoid this, you need to do a onetime program of the entire flash including ECC and use fills for any gaps. This topic is discussed in more detail in this thread: e2e.ti.com/.../372708 or e2e.ti.com/.../555145

    Note that one of several differences between the LC4357/Rm57 devices and all other devices in the Hercules family is that the LC4357/RM57 have ECC enabled permanently and it cannot be disabled.
  • 0 in reply to Chuck Davenport
    Prodigy 60 points
    Thanks for your response, I tried doing this using a linker command to update ECC and it just worked fine. No problem thereafter...