Hello
The input edge timer sample source code is required.
There is no example file in the Peripherals folder. ( edge_count, oneshot_16bit, periodic_16bit, pwm)
I need the edge_time example file.
thanks
[Attach image of desired configuration ]
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Hello
The input edge timer sample source code is required.
There is no example file in the Peripherals folder. ( edge_count, oneshot_16bit, periodic_16bit, pwm)
I need the edge_time example file.
thanks
[Attach image of desired configuration ]
Jame,
I'm going to respond to a few of these because they go to formulating your question for another thread (BTW you did not answer the jitter questions)
Jame shin said:Robert_Q1> What is the ultimate source of your signal?
A1> This is to detect and correct the error of high speed signal output from linear encoder.
Linear encoders don't usually have a duty cycle variation to be measured in my experience. They could add a duty cycle to add some absolute position information but I've not seen it done myself. More usual would be a quadrature arrangement.
Jame shin said:Robert_Q3> What is the range of duty cycles?
A3> A1 The answer is the same.
Duty ratio 0.01% ~ 100% (The smallest unit bit to the maximum bit of the transmission data)
OK, now we have a problem. The spec for detection of an edge is a maximum of 20MHz at 50% duty cycle, your 0.01% is the equivalent to a 100GHz with a 50% duty cycle. This is simply not going to work. I have strong doubts that this will work with any micro or DSP, it's FPGA territory and high end FPGA at that. I don't know if you can clock any FPGA fast enough for that.
Robert