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EK-TM4C1294XL: How to verify if PWM module has actually reset all counters to zero?

Genatco
Guru 55913 points
Part Number: EK-TM4C1294XL
Other Parts Discussed in Thread: SEGGER

Previous posting:
https://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/610763

It seems there might be a possibility the PWM module is not able to reset all counters to zero via Tivaware syntax or the order of such procedure is highly relative. Yet the generators time base via software are made synchronous after a peripheral reset however the 3 generators counters in CCS debug fail to roll count values concurrently to each other.

Could there be an issue using ROM calls to zero the counters?  Is there a specific syntax order or delay period required to ensure all generators are reset to zero count? How can we use CCS debug to ensure all generators counts are reset to zero when count registers are otherwise so varied in counting values. Especially true in light of ICDI updates 1Mhz is considered to slow to even prove equal generator counts occur after peripheral reset.

Perhaps we need Black Hawk XDS200 or Segger high speed debug simulation speeds order to prove yea or neigh?  

http://newscenter.ti.com/2013-08-08-TI-introduces-XDS200-JTAG-emulator-providing-software-designers-a-mid-range-option-for-embedded-designs?keyMatch=xds200 emulators&tisearch=Search-EN-Everything

/* Disable the PWM module */
ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_PWM0);

/* Reset the PWM module zero the counters */
ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_PWM0);

/* Enable the PWM module counters at zero count */
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM0);

/* Pause here until PWM0 module is ready */
while(!(ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_PWM0)))
{
}

/* Divide 120Mhz SYSCLK for 60Mhz PWMCLK */
HWREG(PWM0_BASE + PWM_O_CC) = PWM_SYSCLK_DIV_2;

/* Configure the generators various functions */
//
//

/* Enables the PWM clock to drive the timer/counter of the PWM generators. */
ROM_PWMGenEnable(PWM0_BASE, PWM_GEN_0);
ROM_PWMGenEnable(PWM0_BASE, PWM_GEN_1);
ROM_PWMGenEnable(PWM0_BASE, PWM_GEN_2);
ROM_PWMGenEnable(PWM0_BASE, PWM_GEN_3);

/* Synchronize the PWM generators time bases.  */
HWREG(PWM0_BASE + PWM_O_SYNC) = (PWM_GEN_0_BIT | PWM_GEN_1_BIT | PWM_GEN_2_BIT | PWM_GEN_3_BIT);
  • 0
    Guru 55913 points

    Some engineers might deduce XDS100 (1Mhz) data rate to slow for it to show CCS debug 3 generators have equal count values.

    Ok, does XDS200 (480MBps) data rate show PWM generator counts rolling equal register values, if not why?

    Is any CCS debug SWO/SWD instrument capable to indicate PWM peripheral maintains equal count values when the time base is synchronous between all generators?

    Alternatively can TI do a quick test to confirm all PWM generators do indeed maintain equal count values when the time base is made synchronous after a peripheral reset supposedly zero's all counters? Does the faster XDS200 provide CCS real time SWD/SWO debug information showing equal PWM peripheral rolling counts where the XDS100 can not?

  • 0
    Guru 92251 points

    BP101 said:
    Yet the generators time base via software are made synchronous after a peripheral reset however the 3 generators counters in CCS debug fail to roll count values concurrently to each other.

    Have you measured the PWM outputs with a LSA or oscilloscope and seen that the PWM generators are not synchronised?

    Or is it that the current count values as sampled by the CCS debugger do not appear to be synchronised?

  • 0 in reply to Chester Gillon
    Guru 55913 points

    Hi Chester,

    Chester Gillon said:
    Have you measured the PWM outputs with a LSA or oscilloscope and seen that the PWM generators are not synchronized?

    There is a scope capture in above posted forum link describes chopping pulses move left, center, right (relative) in the 3 phase inverter output.  

    Chester Gillon said:
    Or is it that the current count values as sampled by the CCS debugger do not appear to be synchronized?

    The asserted Sync bit changes 1/0 seem to toggle all together in PWMSYNC register. Difficult to visually see in debug if all roll together or are few milliseconds apart. Yet the 3 generators counts are varied by quite some span. Amit at one time theorized skewed count was TMC123G ICDI (1Mhz) to blame for slow updates CCS debug register view. My reason to ask TI engineers does skewed count self correct with the faster XDS200 emulator.  

  • 0 in reply to Genatco
    Guru 55913 points

    PWM generator count registers are skewed yet the PWM_CTRL global update SYNC bits appear to fire simultaneous. Wondering if the faster XDS200 (480Mbps) would still have the same skew count condition ?