TMS570LC4357: TMS570LC4357: Unexpected Performance Monitoring Unit Data Cache Miss counter ?

Hello,

My previous post https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/614362 got locked unanswered.

I ran a simple memset loop which implements 32bits word copies.

 for (i=0; i<100; i++) {
   memset(fillBuffer, i, 1024*1024);
 }

PMU is turned on with following counters selected :

  0x07, /* Data Writes */
  0x03, /* DL1 Miss */
  0x42, /* Write Backs */

The memset target buffer is located in SDRAM in a cacheable normal non shared area with cacheability attributes set to WriteBack-WriteAllocate.

PMU counters are resetted just before and right after this memset loop.

The memset loop is running to completion without being interrupted. 

The rough theoretical computation is a total amount of 26214400 32bits words written, thus 3276800 cache lines accessed and a very high expected miss rate considering the WriteAllocate policy.

However, the capture of PMU at runtime actually shows a very low data cache miss numbers, while total data write and data cache write back counters seem consistent.

There is no counter overflow as expected.

 Data Write(Overflow), Data Cache Miss(Overflow), Data Cache Write Back(Overflow) => 26214433(0), 351(0), 3202107(0)
 Data Write(Overflow), Data Cache Miss(Overflow), Data Cache Write Back(Overflow) => 26214433(0), 356(0), 3201904(0)
 Data Write(Overflow), Data Cache Miss(Overflow), Data Cache Write Back(Overflow) => 26214433(0), 352(0), 3202353(0)
 Data Write(Overflow), Data Cache Miss(Overflow), Data Cache Write Back(Overflow) => 26214433(0), 350(0), 3203049(0)
 Data Write(Overflow), Data Cache Miss(Overflow), Data Cache Write Back(Overflow) => 26214433(0), 353(0), 3203419(0)
 Data Write(Overflow), Data Cache Miss(Overflow), Data Cache Write Back(Overflow) => 26214433(0), 352(0), 3202068(0)
 Data Write(Overflow), Data Cache Miss(Overflow), Data Cache Write Back(Overflow) => 26214433(0), 346(0), 3203324(0)
 Data Write(Overflow), Data Cache Miss(Overflow), Data Cache Write Back(Overflow) => 26214433(0), 354(0), 3202801(0)

I did not find any errata on the Cortex-R5 Data Cache missPMU event .

Could you please have a look and analyse this issue ?

Thanks,

Franck.