- Ask a related questionWhat is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
A strange situation, i modified ( not so much ) udma_Demo to configure the UART to send one message at a time. it works well for the first message, second one gets transferred immediately too.. however, the third one doesn't get transferred immediately, however, in the following transfer request both of these messages get sent.
void
UARTIntHandler(void)
{
uint32_t ui32Status;
uint32_t ui32Mode;
//
// Read the interrupt status of the UART.
//
ui32Status = ROM_UARTIntStatus(UART0_BASE, 1);
//UARTIntDisable(UART0_BASE);
if (ui32Status == 0x00020000)
{
// do something here..........
ROM_UARTDMADisable(UART0_BASE, UART_DMA_TX);
// Need this step to be able to exit the interrupt.
ROM_UARTIntClear(UART0_BASE, ui32Status);
return;
}
//HWREG(UART0_BASE + UART_O_ICR) = 0x00020000;
//ui32Status = ROM_UARTIntStatus(UART0_BASE, 1);
//
// Clear any pending status, even though there should be none since no UART
// interrupts were enabled. If UART error interrupts were enabled, then
// those interrupts could occur here and should be handled. Since uDMA is
// used for both the RX and TX, then neither of those interrupts should be
// enabled.
//
ROM_UARTIntClear(UART0_BASE, ui32Status);
ui32Status = ROM_UARTIntStatus(UART0_BASE, 1);
//
// Check the DMA control table to see if the ping-pong "A" transfer is
// complete. The "A" transfer uses receive buffer "A", and the primary
// control structure.
//
ui32Mode = ROM_uDMAChannelModeGet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT);
//
// If the primary control structure indicates stop, that means the "A"
// receive buffer is done. The uDMA controller should still be receiving
// data into the "B" buffer.
//
if(ui32Mode == UDMA_MODE_STOP)
{
//
// Increment a counter to indicate data was received into buffer A. In
// a real application this would be used to signal the main thread that
// data was received so the main thread can process the data.
// -------------------------> Set the data recieved flag in Buffer A--->>???
g_ui32RxBufACount++;
//
// Set up the next transfer for the "A" buffer, using the primary
// control structure. When the ongoing receive into the "B" buffer is
// done, the uDMA controller will switch back to this one. This
// example re-uses buffer A, but a more sophisticated application could
// use a rotating set of buffers to increase the amount of time that
// the main thread has to process the data in the buffer before it is
// reused.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT,
UDMA_MODE_PINGPONG,
(void *)(UART0_BASE + UART_O_DR),
g_ui8SigFoxRxBufA, sizeof(g_ui8SigFoxRxBufA));
}
//
// Check the DMA control table to see if the ping-pong "B" transfer is
// complete. The "B" transfer uses receive buffer "B", and the alternate
// control structure.
//
ui32Mode = ROM_uDMAChannelModeGet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT);
//
// If the alternate control structure indicates stop, that means the "B"
// receive buffer is done. The uDMA controller should still be receiving
// data into the "A" buffer.
//
if(ui32Mode == UDMA_MODE_STOP)
{
//
// Increment a counter to indicate data was received into buffer A. In
// a real application this would be used to signal the main thread that
// data was received so the main thread can process the data.
//
g_ui32RxBufBCount++;
//// -------------------------> Set the data recieved flag--->>???
// Set up the next transfer for the "B" buffer, using the alternate
// control structure. When the ongoing receive into the "A" buffer is
// done, the uDMA controller will switch back to this one. This
// example re-uses buffer B, but a more sophisticated application could
// use a rotating set of buffers to increase the amount of time that
// the main thread has to process the data in the buffer before it is
// reused.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT,
UDMA_MODE_PINGPONG,
(void *)(UART0_BASE + UART_O_DR),
g_ui8SigFoxRxBufB, sizeof(g_ui8SigFoxRxBufB));
}
//
// If the UART0 DMA TX channel is disabled, that means the TX DMA transfer
// is done.
//
// The uDMA TX channel must be re-enabled.
//
}
//*****************************************************************************
//
// Initializes the UART0 peripheral and sets up the TX and RX uDMA channels.
// The UART is configured for loopback mode so that any data sent on TX will be
// received on RX. The uDMA channels are configured so that the TX channel
// will copy data from a buffer to the UART TX output. And the uDMA RX channel
// will receive any incoming data into a pair of buffers in ping-pong mode.
//
//*****************************************************************************
void
InitUART0Transfer(void)
{
// Enable the UART peripheral, and configure it to operate even if the CPU
// is in sleep.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);
//
// Enable the uDMA controller error interrupt. This interrupt will occur
// if there is a bus error during a transfer.
//
ROM_IntEnable(INT_UDMAERR);
//
// Enable the uDMA controller.
//
ROM_uDMAEnable();
//
// Point at the control table to use for channel control structures.
//
ROM_uDMAControlBaseSet(pui8ControlTable);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UART0);
//
// Configure the UART communication parameters.
//
ROM_UARTConfigSetExpClk(UART0_BASE, ui32SysClock, 9600,
UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE);
//
// Set both the TX and RX trigger thresholds to 4. This will be used by
// the uDMA controller to signal when more data should be transferred. The
// uDMA TX and RX channels will be configured so that it can transfer 4
// bytes in a burst when the UART is ready to transfer more data.
//
ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
//
// Enable the UART for operation, and enable the uDMA interface for both TX
// and RX channels.
//
ROM_UARTEnable(UART0_BASE);
//ROM_UARTDMAEnable(UART0_BASE, UART_DMA_RX );
ROM_UARTDMAEnable(UART0_BASE, UART_DMA_RX | UART_DMA_TX);
//
// This register write will set the UART to operate in write mode.
//
//HWREG(UART0_BASE + UART_O_CTL) |= UART_CTL_TXE;
//
// Put the attributes in a known state for the uDMA UART0RX channel. These
// should already be disabled by default.
//
ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART0RX,
UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
//
// Configure the control parameters for the primary control structure for
// the UART RX channel. The primary contol structure is used for the "A"
// part of the ping-pong receive. The transfer data size is 8 bits, the
// source address does not increment since it will be reading from a
// register. The destination address increment is byte 8-bit bytes. The
// arbitration size is set to 4 to match the RX FIFO trigger threshold.
// The uDMA controller will use a 4 byte burst transfer if possible. This
// will be somewhat more effecient that single byte transfers.
//
ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 |
UDMA_ARB_4);
//
// Configure the control parameters for the alternate control structure for
// the UART RX channel. The alternate contol structure is used for the "B"
// part of the ping-pong receive. The configuration is identical to the
// primary/A control structure.
//
ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 |
UDMA_ARB_4);
//
// Set up the transfer parameters for the UART RX primary control
// structure. The mode is set to ping-pong, the transfer source is the
// UART data register, and the destination is the receive "A" buffer. The
// transfer size is set to match the size of the buffer.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT,
UDMA_MODE_PINGPONG,
(void *)(UART0_BASE + UART_O_DR),
g_ui8SigFoxRxBufA, sizeof(g_ui8SigFoxRxBufA));
//
// Set up the transfer parameters for the UART RX alternate control
// structure. The mode is set to ping-pong, the transfer source is the
// UART data register, and the destination is the receive "B" buffer. The
// transfer size is set to match the size of the buffer.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT,
UDMA_MODE_PINGPONG,
(void *)(UART0_BASE + UART_O_DR),
g_ui8SigFoxRxBufB, sizeof(g_ui8SigFoxRxBufB));
//
// Put the attributes in a known state for the uDMA UART0TX channel. These
// should already be disabled by default.
//
ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART0TX,
UDMA_ATTR_ALTSELECT |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
//
// Set the USEBURST attribute for the uDMA UART TX channel. This will
// force the controller to always use a burst when transferring data from
// the TX buffer to the UART. This is somewhat more effecient bus usage
// than the default which allows single or burst transfers.
//
ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_UART0TX, UDMA_ATTR_USEBURST);
//
// Configure the control parameters for the UART TX. The uDMA UART TX
// channel is used to transfer a block of data from a buffer to the UART.
// The data size is 8 bits. The source address increment is 8-bit bytes
// since the data is coming from a buffer. The destination increment is
// none since the data is to be written to the UART data register. The
// arbitration size is set to 4, which matches the UART TX FIFO trigger
// threshold.
//
ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_8 |
UDMA_DST_INC_NONE |
UDMA_ARB_4);
//
// Set up the transfer parameters for the uDMA UART TX channel. This will
// configure the transfer source and destination and the transfer size.
// Basic mode is used because the peripheral is making the uDMA transfer
// request. The source is the TX buffer and the destination is the UART
// data register.
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, g_ui8SigFoxTxBuf,
(void *)(UART0_BASE + UART_O_DR),
sizeof(g_ui8SigFoxTxBuf));
// Now both the uDMA UART TX and RX channels are primed to start a
// transfer. As soon as the channels are enabled, the peripheral will
// issue a transfer request and the data transfers will begin.
//
ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0RX);
ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0TX);
//
// Enable the UART DMA TX/RX interrupts.
//
ROM_UARTIntEnable(UART0_BASE, UART_INT_DMATX | UART_INT_DMARX);
//
// Enable the UART peripheral interrupts.
//
ROM_IntEnable(INT_UART0);
}
void SigFoxDMASend(const uint8_t *pui8Buffer, uint32_t ui32Count)
{
int index = 0;
//Clear the Previously recieved data in both Buffers
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_PRI_SELECT,
UDMA_MODE_PINGPONG,
(void *)(UART0_BASE + UART_O_DR),
g_ui8SigFoxRxBufA, sizeof(g_ui8SigFoxRxBufA));
//
// Set up the transfer parameters for the UART RX alternate control
// structure. The mode is set to ping-pong, the transfer source is the
// UART data register, and the destination is the receive "B" buffer. The
// transfer size is set to match the size of the buffer.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0RX | UDMA_ALT_SELECT,
UDMA_MODE_PINGPONG,
(void *)(UART0_BASE + UART_O_DR),
g_ui8SigFoxRxBufB, sizeof(g_ui8SigFoxRxBufB));
for (index = 0; index < UART_RXBUF_SIZE; index++)
{
g_ui8SigFoxRxBufA[index] = 0;
}
for (index = 0; index < UART_RXBUF_SIZE; index++)
{
g_ui8SigFoxRxBufB[index] = 0;
}
// Clear the Transmission buffer
for (index = 0; index < UART_TXBUF_SIZE; index++)
{
g_ui8SigFoxTxBuf[index] = 0;
}
// Next step is to move the new data to the transmission Buffer
uint32_t counter8 = 0;
while(ui32Count--)
{
g_ui8SigFoxTxBuf[counter8]= pui8Buffer[counter8];
++counter8;
}
// Enable the transfer function
//
// Start another DMA transfer to UART0 TX.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, g_ui8SigFoxTxBuf,
(void *)(UART0_BASE + UART_O_DR),
sizeof(g_ui8SigFoxTxBuf));
//
// The uDMA TX channel must be re-enabled.
ROM_UARTDMAEnable(UART0_BASE, UART_DMA_RX | UART_DMA_TX);
ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0TX);
}
int main(void)
{
//
// Initialize the uDMA UART transfers.
//
InitUART0Transfer();
delayms(10);
int ui16Idxo = 0;
unsigned char result[UART_RXBUF_SIZE];
for(ui16Idxo = 0; ui16Idxo < UART_RXBUF_SIZE; ui16Idxo++)
{
result[ui16Idxo] = g_ui8SigFoxRxBufA[ui16Idxo];
}
char bluemoon[]="AT\r";
SigFoxDMASend (bluemoon, 4);
delayms(10);
ui16Idxo = 0;
for(ui16Idxo = 0; ui16Idxo < UART_RXBUF_SIZE; ui16Idxo++)
{
result[ui16Idxo] = g_ui8SigFoxRxBufA[ui16Idxo];
}
//Start another DMA transfer to UART0 TX.
unsigned char bluemoon1[]="AT$I=10\r";
// SigFoxDMASend (bluemoon1, 9);
delayms(10);
//Start another DMA transfer to UART0 TX.
//Start another DMA transfer to UART0 TX.
SigFoxDMASend (bluemoon1, 9);
delayms(10);
SigFoxDMASend (bluemoon, 4);
delayms(10);
SigFoxDMASend (bluemoon, 4);
delayms(10);
}
