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CCS/TM4C1294NCPDT: TM4C1294XL Launchpad SoftSPI SPI max clock rate?

Part Number: TM4C1294NCPDT

Tool/software: Code Composer Studio

I'm using TM4C1294XL Launchpad in one project with six to seven SPI interfaces, therefore I'm using Tivawave softSPI driver library. My question, what is the max clock rate the softSPI core can support?

Thanks,
Guoping

  • May it be asked if you've considered - instead of 6-7 (different) SPI channels - deploying (just one)  SPI Module?      Your use of,  "GPIO Controlled, Individual, SPI Slave Chip Selects" enables ONE SPI Module to "transact w/multiple Slaves" - provided the SPI Module's "FSS" signal is disabled.    (and replaced by unique GPIO outputs)

    Firm/I have done "just this" - but I recall  FIVE Slaves - as our implementation.    (more were likely to work)

    This method enables you to transact at FULL SPI Module Clock Rate - surely a substantial improvement over (your earlier - far slower) "Soft SPI."

    In the event that (certain) of your Slaves demand "different SPI protocols" you may:

    • alter the SPI Module's "Set-Up" to comply - on a device basis
    • employ an additional SPI Module - "Set-Up" for that (other) protocol     (this method (still) should reduce the number of SPI Modules required)

  • thank you, this will work for some SPI channels since they are sharing the same protocol. Definitely it will save some of my troubles.
  • You have "Verified" your post - which in fact did not, "Solve your Issue or Problem." Protocol here dictates that you "Verify" the Answering Post - not your own!
  • Thanks, No, it will not resolve the original question. Your answer will help me, I'll go different way (using dedicated SPI).
  • Do look again to what's been added to that initial post.

    There was NO Indication of "varying SPI protocols" included w/in your first post.     I've properly "adapted" to that Newly Introduced Demand, now...