TMS570LC4357: Entry condition in low power mode and system module global low power request

Hi Franck,

To enter low power mode (Doze, Snooze, Sleep), the 4th step is required. Application needs to write to the clock domain disable register (CDDIS) to disable the GCLK1/2 (CPU clock), HCLK1/2 (system clock), VCLKP (peripheral VBUS clock), VCLK2/3 (peripheral VBUS clock), and VCLKA1/2/4 (asynchronous peripheral VBUS clock). All these domains must be disabled in order to be considered in doze /snooze/sleep mode. The RTICLK domain may or may not be disabled. Doze/Snooze modes are normally used in conjunction with an RTI in order to wake up the device periodically from within.

Bit 0 of CDDIS is to disable the GCLK only.

When system wants to go into low power mode it requests clock stop to DMA through asserting clock_stop_request signal high , in response DMA will stop its transactions at the next arbitration boundary for all transactions and assert clock_stop_ack signal low. If there is no pending channel, the DMA will immediately respond clock stop acknowledge.

When system starts waking up, it will de-assert clock stop request signal low and start clocking DMA. In response DMA should wait for the clock and than de-assert clock stop acknowledge signal high.