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Original question:

RM48L952: RM48xx SPI Slave mode,

RM48L952: RM48xx SPI Slave mode not working,

paddu2017
Expert 2885 points
Part Number: RM48L952

Hi,

I am creating a new thread here because there is no response to the below E2E for a week.
e2e.ti.com/.../2508776

Do we require to use MibSPI's CS line in Slave mode to read/write with different size and different group?
In our application RM48L952 is used as a SPI slave 3 pins only(without CS).
We would like to know what should be taken care of in order to
implement SPI read/write with different size of data in Slave mode?

I believe in case of master mode, we can read/write with different size if we
change the group, but in this case we are not able to start the communication
even if we change the group(except for group0).The CSHOLD bit is set to 1.
We are trying this on a LaunchPad.

Below E2E mentions that In MIBSPI Slave mode, the CS lines are used to specify which Transfer Group,
so is it mandatory to use CS line to read/write with different size and different group?
e2e.ti.com/.../1012758

PLease let me know do we need CS to implement this?

Best Regards
paddu

  • 0
    TI__Guru**** 197056 points
    Hello Paddu,

    When operating in slave mode, the MibSPI uses the chip-select pins 0 to 3 to generate a trigger to the corresponding Transfer Group.

    For example, putting 0000 on the chip-select pins triggers Transfer Groups 0 and putting 0001 triggers TG1. When the value 1111 is set to the chip-select, the MibSPI is deselected, that is Transfer Group 15 is not available in slave mode. The remaining chip-select pins should stay in GPIO mode.

    In slave mode, the fields like trigger source and trigger event are not taken into account by the sequencer. Only the SPICS pins can trigger a Transfer Group. The chip-select trigger operates as a level-sensitive trigger.

    However, when the MibSPI is in 3-pin or 4-pin with SPIENA mode, just one Transfer Group can be triggered and it is restricted to Transfer Group 0 (TG0).