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Original question:

Increasing I2C Pin driver levels on TM4C129x devices.

RTOS/TM4C1294NCPDT: Change I2C pins Drive Strength on TM4C129x devices.

IgDor
Intellectual 280 points
Part Number: TM4C1294NCPDT

Tool/software: TI-RTOS

I need to change the current strength of I2C bus pins.

I tried to do it this way:

ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C8);

ROM_GPIOPinConfigure(GPIO_PA2_I2C8SCL);

GPIOPadConfigSet(GPIO_PORTA_BASE, 2, GPIO_STRENGTH_12MA, PIO_PIN_TYPE_STD);

ROM_GPIOPinTypeI2CSCL(GPIO_PORTA_BASE, GPIO_PIN_2);

ROM_GPIOPinConfigure(GPIO_PA3_I2C8SDA);

GPIOPadConfigSet(GPIO_PORTA_BASE, 3, GPIO_STRENGTH_12MA, GPIO_PIN_TYPE_OD);

ROM_GPIOPinTypeI2C(GPIO_PORTA_BASE, GPIO_PIN_3);

 

And then I checked the PAD configuration:

GPIOPadConfigGet(GPIO_PORTA_BASE, 2, &A2Strength, &A2PinType);

GPIOPadConfigGet(GPIO_PORTA_BASE, 3, &A3Strength, &A3PinType);

 

The "Strength" of pins always 1, it does not change when changed the  GPIO_STRENGTH_xMA parameter.

.Also I checked if something changed by scope, nothing(rise time and low level) changed.

 

Does it possible to change Drive Strength for I2C pins?

Thanks in advance.

  • 0
    Guru 55913 points
    Hi IgDor,

    Only high speed GPIO pads per datasheet 10.2 can produce >2ma drive strength but then states only pad PJ1 is slow pad (APB). Question then becomes why 10.2 does not relate fast pads to fast AHB_GPIO pins in general.

    Anyway that's how pin strength makes sense relative to GPIO bus speed in my opinion.
  • 0
    TI__Guru 72500 points

    The GPIOPadConfigSet() functions must be called after the GPIOPinTypexxx() functions.

        GPIOPinTypeI2CSCL(GPIO_PORTA_BASE, GPIO_PIN_2);
    GPIOPinTypeI2C(GPIO_PORTA_BASE, GPIO_PIN_3);

    GPIOPadConfigSet(GPIO_PORTA_BASE, 2, GPIO_STRENGTH_12MA, GPIO_PIN_TYPE_STD);
    GPIOPadConfigSet(GPIO_PORTA_BASE, 3, GPIO_STRENGTH_12MA, GPIO_PIN_TYPE_OD);

  • 0 in reply to Bob Crosby
    Intellectual 280 points

    Hi Bob.

    Thank for the advice. But I also found that the second parameter(pin number) in GPIOPadConfigSet function should be the pin's "define" - GPIO_PIN_x.

    It's strange, in GPIOPadConfigGet function it should be just pin number, but in a GPIOPadConfigSet function it should be pin's "define".

     

    Now it works and looks like this:

    Set parameters:

    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C2);

    ROM_GPIOPinConfigure(GPIO_PL1_I2C2SCL);

    ROM_GPIOPinConfigure(GPIO_PL0_I2C2SDA);

    ROM_GPIOPinTypeI2C(GPIO_PORTL_BASE, GPIO_PIN_0);

    ROM_GPIOPinTypeI2CSCL(GPIO_PORTL_BASE, GPIO_PIN_1);

    GPIOPadConfigSet(GPIO_PORTL_BASE, GPIO_PIN_1, GPIO_STRENGTH_12MA, GPIO_PIN_TYPE_STD);

    GPIOPadConfigSet(GPIO_PORTL_BASE, GPIO_PIN_0, GPIO_STRENGTH_12MA, GPIO_PIN_TYPE_OD);

     

    Get parameters:

    GPIOPadConfigGet(GPIO_PORTL_BASE, 0, &L0Strength, &L0PinType);

    GPIOPadConfigGet(GPIO_PORTL_BASE, 1, &L1Strength, &L1PinType);

     

    Another strange that getted STRENGTH parameters are different for different pins. E.g if you set GPIO_STRENGTH_12MA, and then get it for the part of pins it is 119, and for others it is 23.

     

    Best regards.

  • 0 in reply to Bob Crosby
    Guru 55913 points

    Another odd question is datasheet suggests >2ma drive strength is only produced by fast AHB_GPIO pins, not by slow GPIO_APB pins.

    Table 27-35. Slow GPIO Module Characteristics only list 2ma drive strength no higher. That said how can standard GPIO pins produce >2ma drive strength?

  • 0 in reply to Genatco
    Intellectual 280 points
    TM4C1294NCPDT has only one Slow GPIO pad - PJ1, others are Fast GPIO pads.
    see. 10.2 Pad Capabilities of Data Sheet.
  • 0 in reply to IgDor
    Guru 117855 points

    Poster IgDor has indeed noted an 'unusual' inconsistency between the 'Parameter treatment' - between the API's 'GPIOPadConfigGet() vs. 'GPIOPadConfigSet().'      That was 'highly' unexpected - and (almost) certain - to 'trip-up' many.      (and perhaps be added to the expanding list of 'things to do' (yet after the (proper) restoral of LIKE!)

    IgDor's report of 'Strength Parameters' as also being 'strange'  - proves true - yet those values are (very) well detailed - as shown here:  (this via file, 'gpio.h'

    //*****************************************************************************
    //
    // Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter,
    // and returned by GPIOPadConfigGet in the *pui32Strength parameter.
    //
    //*****************************************************************************
    #define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
    #define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
    #define GPIO_STRENGTH_6MA 0x00000065 // 6mA drive strength
    #define GPIO_STRENGTH_8MA 0x00000066 // 8mA drive strength
    #define GPIO_STRENGTH_8MA_SC 0x0000006E // 8mA drive with slew rate control
    #define GPIO_STRENGTH_10MA 0x00000075 // 10mA drive strength
    #define GPIO_STRENGTH_12MA 0x00000077 // 12mA drive strength

  • 0 in reply to cb1_mobile
    Intellectual 280 points
    I checked the STRENGTH for all 7 I2C buses that I use. For 2ma and 4ma it's O.K. all pins have STRENGTH 1 and 2 respectively, but from 6ma and higher there is difference. E.g. for 12ma 5 pins have 0x77 and others 9 - 0x17
  • 0 in reply to IgDor
    Guru 117855 points

    You are - once more - to be commended for 'diligence.'    Even being 'here' forever - I cannot recall another - broaching this subject - certainly not with the skill & depth you've displayed.

    Beware (always) single board (and here) single chip - Anomaly!     I'd repeat this test across 3-5 additional MCUs - to see if your results prove (almost) 'universal.'

  • 0 in reply to IgDor
    Guru 55913 points
    Not the way it sounds at first, read it slowly several times. What it is saying, PJ1 by design can only be slow 2ma. You must add (GPIO_PORT#_AHB_BASE) into the call to select AHB data bus aperture and GPIOSLR slew rate register.
  • 0 in reply to Genatco
    Guru 55913 points
    According to table 27-34 the higher >2ma drive strength (slew rate) is only available to AHB defined pins in table 27-34.

    My very question last week Tivaware GPIOPinConfigure() seemingly does not properly select the AHB bus for the peripherals GPIO(x), seemingly sets APB aperture by default. Assume was for TM4C123 devices SYSCTL_GPIOHBCTL register (0x400FE06C) does not exist in TM4C129x, per a datasheet search for registers existence.

    Even when AHB_BASE was being added into the call GPIOPinConfigure() the aperture selected ends up APB. That is according to the datasheet actually be correct in table 27-34/35.