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TMS570LS3137: 64Bit Timer counter

Part Number: TMS570LS3137

Hello,

I'm trying to get a 64bit timer counter going. 

Right now, I'm just configuring the counter0 as an upcounter at 45Mhz, and each time it overflows, manually writing counter1's FRCx, and returning the 64bit value as follows:

void rtiNotification(uint32 notification)
{
    switch (notification) {
    case rtiNOTIFICATION_COUNTER0:
        ++rtiREG1->CNT[1].FRCx;
        break;
    }
}

uint64_t getTime() {
    _disable_IRQ();
    uint32_t frcLow = rtiREG1->CNT[0].FRCx;
    uint32_t frcHigh = rtiREG1->CNT[1].FRCx;

    _enable_IRQ();
    return (uint64_t) (((uint64_t)frcHigh << 32) | (uint64_t)frcLow);
}
// resolution per tick = 1/f * NsInSec
#define RES (uint64_t) (1.0/45000000 * 1000000000)  
void delay(uint64_t delay_ns) {
    if (delay_ns > RES) {
        uint64_t start = getTime();
        uint64_t ticks = (uint64_t)(delay_ns/RES);

        while ((getTime() - start) < ticks);
    }
}

int main(void)
{
    rtiInit();
    rtiEnableNotification(rtiNOTIFICATION_COUNTER0);
    _enable_IRQ();
    rtiSetPeriod(0, 0xffffffff);
    rtiStartCounter(rtiCOUNTER_BLOCK0);

    while (1) {
        delay(30000000000);   // 30 sec in nanosecs
        ledToggle();
        //pinToggle();
    }
}

questions:

* is there a better way to do this?

* Saw this in the datasheet that confused me a little bit, please explain in simpler words (I'm having a hard time what this does)?

RTI Up Counter 0 Register (RTIUC0)

Description: Up counter 0. This register holds the current value of the up counter 0 and prescales the RTI clock. It will be only updated by a previous read of free running counter 0 (RTIFRC0). This method of updating effectively gives a 64-bit read of both counters, without having the problem of a counter being updated between two consecutive reads on up counter 0 (RTIUC0) and free running counter 0 (RTIFRC0). A read of this counter returns the value of the counter at the time RTIFRC0 was read. A write to this counter presets it with a value. The counter then increments from this written value upwards

Thank you for your support!

KB

  • KB,

    Let me answer the second question first: the RTI includes two counters, each 32-bit wide. The CPU can only read one 32-bit value at a time from the RTI register frame. This means that there is a non-zero delay between when the CPU reads the first 32-bit value and when it reads the second 32-bit value. This would be wrong whenever you are using the RTI to time-stamp any event (CAPEVT). This is the reason why a special counter capture mechanism is implemented to be able to accurately read the 64-bit time-stamp using the two counters - you read from the free-running counter first, which freezes the Up Counter at this instant so that the application can read out the up counter value in a subsequent read.

    Hope this helps.

    Regards,
    Sunil