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TMS570LS3137: RTI: overflow, counter reset and compare ticks

_MM_
Expert 1995 points
Part Number: TMS570LS3137


Hello,

I have two doubts about the behavior of the RTI:

1) What happens in case of overflow (0xFFFFFFFF) of a counter? Is the count reset? Does the program go to stall/abort?

2) Does a intended/unintended reset of one of the counters (e.g. by executing rtiResetCounter) impact with the generation of the RTI interrupts at the compare frequency?

Thanks ahead for a reply.

Regards.

  • 0
    TI__Guru**** 198766 points

    Hello,

    1. If the overflow interrupt is enabled, the overflow interrupt will be generated when FRC counter reaches to 0xFFFFFFFF. Then the FRC counter starts count from 0x0

    2. rtiResetCounter clears the UC register and FRC register, but doesn't change the value of compare registers (CPUC, and UDCP, COMP), so it doesn't impact the frequency or period of the interrupts.

  • 0 in reply to QJ Wang
    Expert 1995 points

    Hello,

    Thanks for the answers.

    1) Ok. Clear now.

    2) According to the TRM, the interrupts are generated when RTIFRCx matches with RTICOMP. If I reset RTIFRCx just a bit before this match, that interrupt will be not generated at the same at that instant (compromising the periodicity of the interrupt generation).

    Are there maybe in between those registers you mentioned copies of RTIFRCx that are not actually reset even if rtiResetCounter runs ? Otherwise, I cannot get how it is possible to preserve the periodicity of the interrupts.

    Regards.

  • 0 in reply to _MM_
    TI__Guru**** 198766 points

    Hi,

    Yes, resetting the UC and FRC registers will postpone the generation of next compare interrupt, but I won't affect the following interrupt frequency.

    rtiResetCounter() doesn't change the value in compare register (RTICOMP), update compare register (RTIUDCP), and compare up counter (RTICPUC), so the interrupt frequency is not changed.