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Original question:

TM4C1294KCPDT: Analog comparator C0+ threshold

TM4C1294KCPDT: Analog comparator C0+ threshold

Genatco
Guru 55913 points
Part Number: TM4C1294KCPDT
Other Parts Discussed in Thread: INA240

What should be done with unused analog comparator inputs C1+, C2+ input pins when external reference is provided by C0+ for all compactors?

Can these unused inputs if left floating lead to random noise on the comparator Cn- input structure? Does the comparator block ground unused Cn- pins internally when C0+ is configured to provide external +VREF threshold via GPIO port C6?  

  • 0
    TI__Guru 72500 points

    To avoid capacitively coupling noise across the analog pass gate, I suggest that you not configure pins for C1+ and C2+. That way there are two passgates between signals on the pin and the voltage comparator. The first is the input signal mux, and the second is the analog passgate in the analog comparator module. Then it should be safe to use these pins as GPIO or for a different peripheral. If the pins are unused, the preferred practice is to ground them.

  • 0 in reply to Bob Crosby
    Guru 55913 points

    Hi Bob,

    Bob Crosby said:
    I suggest that you not configure pins for C1+ and C2+.

    That is sort of the point as the pins are not being configured but are still part of the comparator block internally.

    So the +ve inputs are tristated and adjacent analog signals on the MCU package pins can not enter the IN+ input?

    Oddly adding an external 10k WPD to the C2- analog input helps reduce false triggering but C2- is most always the offender of the three OR'd MnFault sources. There is still a small amount of current flow in the last OR'd M2fault source, regardless of analog comparators XOR being configured as OD. 

  • 0 in reply to Bob Crosby
    Guru 55913 points
    Hi Bob,

    Appologize for late response to answer. So some of your assessment of transient was partially correct where C0+ VREF bypass circuit had some effect on the threshold of C2- input. Typically a 0.01uf cap near MCU pin is sufficient to stop threshold triggering yet it became more obvious not always. So making CoN XOR outputs OD seemed to help in that regard but not entirely.

    Long story short the C0+ bypass 0.1uf reduced the C2- input trigger point threshold roughly 450mv. The bad thing noticed is the same perceived fault condition on C2- input may lock the MCU. Perhaps the INA240 output is marginal at times yet the signal appears well during runs compared to others. We even have Johanson EMI ceramic filters on the differential inputs of all INA240.