SPNU563 "7.8.2.2 ECC Data Correction Diagnostic Mode 7: DIAGMODE = 7" documents the following test procedures:
1. Branch to a non-flash region to execute this sequence.
...
4. Set DIAG_TRIG to 1 in the FDIAGCTRL register.
5. Select the appropriate port in which the flip is desired using the DIAG_BUF_SEL field of the
FDIAGCTRL register. Only legal values are 0 for port A and 4 for port B.
6. Do a port A or B read to the desired address. The L2FMC will XOR the data and ECC with
FEMU_DxSW and FEMU_ECC respectively for this read before delivering it to the CPU. No further
reads are affected by this diagnostic.
"Branch to a non-flash region" sounds simple enough, but it's actually very cumbersome on TMS570, when testing DED:
- Creating an intentional DED error in this self-test will trigger ESM2 error (unmaskable!) + FIQ.
- FIQ firing will access the vector table at address 0x0, which is normally flash address space.
Using MEMSW to remap the vector table to RAM is an option, but very cumbersome. Are there any other ways to avoid access to flash on FIQ?
Or maybe look at this problem another way. Do we really need to avoid misc. flash access throughout the entire test or just during some critical steps? E.g., consider the following code (assume executing out of RAM):
while (testing many DED combinations....) {
DSB; // ensure all accesses to flash (E.g., from vector table read) are complete
Set DIAG_TRIG to 1 ...
Select the appropriate port ...
Do a port A or B read to the desired address ...
// FIQ fires on read! Vector table is read from flash, but that's ok?
Verify DED detection / appropriate error status...
}
Would the above be guaranteed to work, since no non-test flash access occurs between DIAG_TRIG getting set and the test flash read?
