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TM4C1294KCPDT: ADC0 acquisition point

Genatco
Guru 55913 points
Part Number: TM4C1294KCPDT
Other Parts Discussed in Thread: INA240, EK-TM4C1294XL

Attempting to get correct acquisition from INA240 output signal near 100kHz CMRR, 10us settling time. Yet that settling appears much better in signal capture (below)  on ANIx filter capacitor. Seemingly this is an impossible task without multiplying sample array results via PWM duty cycles. Different NSH values have no direct affect upon digital conversions producing higher unsigned integers relative to increasing analog magnitude that is not moving sample acquisition points proportionately with those changes. Other words the sample range never moves from zero volts up to full scale 3.1v in a linear manner and following analog signal behavior using samples as a DMM current meter easily achieves.

ADC0: 15-30Mhz ADCCLK 1-2MSPS 2x Hardware averaging. Triggered sample points allowing for various analog settling times makes no difference in digital values always representing LSB versus linear increase being made into MSB in order to achieve ADC full scale. Reading of sample array values into integers are not being weighted relative to increasing acquisition magnitudes in the analog signal. Odd part is other analog channels are converting analog peaks from dividers into digital display and maintaining some accuracy in acquisition points in the volt range.

Why is the SAR ADC not capable to properly convert to digital the peaks in the simple very slow 80us signal?

Note: Error is roughly 1/4 LSB and Cext (peak) never exceeds 1/2 LSB blue line.

  

  • 0
    TI__Guru 72500 points
    Are you getting the proper value if you replace the output of the INA240 with a DC signal?
  • 0
    Guru 117855 points

    Those (are) crystal clear screen-caps - if (not) 'teased and/or massaged' - I'd award a 'LIKE.'

    That said - there IS an element of concern - w/in your writing:   (box captures)

    Did you (really) intend to protest '1/2 lsb' ... was not '1/2 of PEAK' intended?

    Beyond that - vendor's Bob raises a good point.    

    As it is 'uncertain' that he recalls yours is a 'Live BLDC Motor Current Monitoring' - it 'WOULD' prove useful for you to, (temporarily) 'replace the INA240's output w/a 'Fixed, low-Z, output voltage!'     (Without  the motor running - which would substantially 'quiet things' - thus grant the MCU's ADC  'the best chance to (properly) respond...')

    As 'KISS' always directs - 'Small, Focused, Measurable' (tested & confirmed) - 'Steps toward your end objective!'

  • 0 in reply to Bob Crosby
    Guru 55913 points
    Hi Bob,

    That is sort of the point that a non periodic analog signal conversion to digital being no problem. The capture is not of the original signal and represents open loop amplifier gain being filtered reducing EMI. Even if signal being very limited filtered (200pf) the same conversion results occur but with a lot more periodic single peaks. There are actually 3 AINx channels same basic signal calculated via 3 low pass filters passing only RMS (.707) peak values into the PWM duty cycle control blocks.

    Remove PWM duty cycle multiplier from the returned array value the signal remains along first 50mV inside 10mV/A. So 0V up to first steady current sample (1.2A) the array[3] read integers remain under 100mv up to the logical acquisition peak (840mv) of MSB. Text states amplifier output setting required to be 1/2 to 1/4 of LSB for SAR to achieve proper acquisition.
  • 0 in reply to Bob Crosby
    Guru 55913 points

    BTW the same results occur upon several EK-TM4C1294XL that were tested with the same 240-A2 amplifiers. Now back tracking to remove the patch improve precision SAR results. Seems impossible to achieve even via reduced gain of newer 240-A1 monitors, 10mV/A the 840mv 1/2 LSB should convert close to 8.4A without any monkey business.

  • 0 in reply to cb1_mobile
    Guru 55913 points

    If your truly interested why 1/2 LSB settling even though it seems an MSB issue, PDF below link is an excellent 2018 source. 

    /cfs-file/__key/communityserver-discussions-components-files/908/TI_2D00_Analog-Engineers-circuit-cook-book-slyy138.pdf

  • 0 in reply to cb1_mobile
    Guru 55913 points

    Recent reading that 1/2 LSB, better being 1/4 LSB (resolution) refers to sample acquisition voltage inside charge sharing (Pg.7) or C-external (vertical lines in signal).  Hercules PDF Charles presented shows  SAR  in detail explaining LSB resolution thresholds. Even sharing with only 1nf CEXT, charge sharing should refine but sample acquisition did not improve along with finer LSB resolution. Hercules SAR shows conversion occurs peak of each Cext charge cycle. Check capture post again Cext was 22nf extending charge recovery time across 80us.  

    /cfs-file/__key/communityserver-discussions-components-files/908/TI_2D00_Analog-ADC-source-impedance-spna118b.pdf

  • 0 in reply to Bob Crosby
    Guru 55913 points

    Hi Bob,

    After a bit of digesting this issue trying various filters, values Cext series Rs, a pattern has appeared. The signal having both low/high attributes relative to full scale (3.1v) is being rescaled. Oddly FIFO results always include 1/4 LSB values (capture) relative to analog GND there by compressing the entire signal magnitude, rescaling the linear results values of 1/4 LSB samples. Even if the 240 output bias is made +1.225v or +1.65v the same compression occurs stripping MSB as if it did not exist. Software drains (clears) the FIFO results each interrupt cycle so it starts from 0x0 each new sample.

    That said it would seem the 1/4 LSB resolution integer bit values (yellow box) are not being shifted during conversion into MSB bit positions relative to NSH acquisition points. Perhaps default NSH 0x4 is holding the required FIFO shift (LSB->MSB) above 1/2 LSB forcing the true results into error status. Multiplying PWM duty cycle by FIFO array[] results tells us bit shift (circular) of 1/4 LSB sample integers into correct MSB bit positions in circular FIFO is not occurring.

    Seemingly the reason 1/2 LSB error FIFO shifting (Cext charge sharing) is not so obvious with pure DC signal is the FIFO results always return 1/2 LSB (steady state) values. That hides the 1/2 LSB error by adjusting software low pass filtering to compensate until the correct DC digital value is achieved. Basically software morphs 1/2 LSB FIFO error into MSB shifted results by integer manipulation of each sample value via software low pass filtering. It would seem some kind of errata in the converter or the FIFO bit clock rate is not at least 16x the serial baud dot relative to NSH sample clocking.

    Seemingly this thread reveals an ADC clocking issue inflicting circular FIFO. Perhaps Charles can have a look at why the Cext 1/4 LSB results in above signal are not being shifted into MSB bit positions relative to cADC charge voltage of the 3v3 full scale?

  • 0 in reply to cb1_mobile
    Guru 55913 points
    CB1 how you pull that rabbit out of hat remain still on head? Yet answer moves conversation further into the black hole of singularity.

    The 1/2 LSB versus 1/4 LSB resolution results not shifting bits into MSB in FIFO relative to Cext amplitude. Seemingly one reason why multiplying duty cycles by FIFO filtered results produce near but not precision sample results.
  • 0 in reply to Genatco
    Guru 117855 points

    My (only) thought was that 'ANY VENDOR' - producing a 'mixed-signal' device - is 'almost SURELY' unable to realize 'analog conversion results' - which approach (anywhere NEAR) 1/2 lsb ACCURACY of Full ADC Scale.     Almost everything (ELSE) - being presented here - is beyond (my) 'limited grasp.'     Although I will 'offer up'  - any: 1/2, 1/4, or 1/8 lsb 'variation' - of conversion's voltage peak - unless such (specifically targets) 'Known ADC JITTER' - to my mind - proves of (limited) value.

    As reported here (many times) most always the '3 least significant MCU's ADC (bits)' - suffer 'jitter' - which the various HW AND SW 'AVERAGING TECHNIQUES' - strive to mask.   (really, conceal)    Adding 'massive' conversion time - in the attempt to 'resolve jitter' - inflicts a 'trade-off'  -  which NOT ALL can accept...

    And again - such is a, 'Reflection of REALITY' - surely NOT a 'vendor knock!'     And ALL of the competing ARM MCUs - my firm has employed and/or examined - behave in a highly similar (i.e. 3 lsb 'dancing' ) fashion...