Part Number: TM4C1294KCPDT
Other Parts Discussed in Thread: TIDA-00909, INA240
Previous thread said it would seem 1/4 LSB resolution FIFO bit values (yellow box) are not being shifted during conversion into MSB bit positions relative to NSH acquisition points. Perhaps default NSH 0x4 is holding the required FIFO shift (LSB->MSB) above 1/2 LSB forcing the true results into error status. Multiplying PWM duty cycle by FIFO array[] results tells us bit shift (circular) of 1/4 LSB sample integers into correct MSB bit positions in circular FIFO is not occurring. Otherwise we have digital compression relative 3.3v full scale from the resulting FIFO value 1/2 LSB error being read into the software Array[].
Seemingly the reason 1/2 LSB error FIFO shifting (Cext charge sharing) is not so obvious with pure DC signal is the FIFO results always return 1/2 LSB (steady state) values. That hides the 1/2 LSB error by engineers adjusting SW low pass filtering to compensate for 1/2 LSB error until the correct DC digital value is achieved. Basically software morphs 1/2 LSB FIFO error into MSB shifted results by integer manipulation of each sample value via software low pass filtering. It would seem some kind of converter errata or FIFO clock rate not being 16x the serial bit rate relative to NSH sample clocking.
Can engineering have a look at why the Cext 1/4 LSB results (yellow box) are not being shifted into MSB bit positions as expected they should? Seemingly cADC or NSH charging do not produce 1/4 LSB FIFO results consistent with or to 3v3 full scale unless perhaps the AINx signal has mostly linear steady state attributes. Only a hypothesis at this point sequencer samples (yellow box) actually represent 1/2 LSB error shifted into FIFO incorrectly when we are expecting 1/4 LSB results to be circular shifted into higher MSB bit positions relative to 3v3 full scale.
The 840mv (Csamp) started much lower value (50mv) at the beginning of sampling, slowly rising 840mv over several seconds in capture below. That slow linear rise is not being transferred into the FIFO returned results but maybe total of 100mv if even. Yet the charge sharing peaks Cext are present in the FIFO results without linear slope and rise. ADC0: 60/30Mhz ADCCLK, single ended AINx inputs.
