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TM4C1294NCPDT: Catastrophic device failure

Part Number: TM4C1294NCPDT

Hello,

Further queries relating to this issue;

we need to understand more on the manifestation of ESD failures in the microprocessor.

We have just found another forum entry – see

http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/p/318646/1735906?pi239031350=3

 

Amit here is referring to adding capacitors on the USB as per an errata – however we cannot find the information he is referring to, can you supply any info regarding capacitor selection?

 

I am looking at a couple of ideas (not sure if they will help us)

    1. We use USB connected to PB0&1 (followed the recommended guides) – but I will look at adding isolation – maybe a buffer IC -  of the signal lines to the port.
    1. Adding current limiting resistors to I/O lines.

 

I will have three failed uP next week – unfortunately others have been dumped. Would we be able to arrange De-Capping?

 

Can you help?

 

 

Regards

Linda

  • For the climate change deniers refusing to believe mankind plays any part in the issue..

    My report of VBUS via PB1 pin of OTG port being damaged after MCU was depowered and leaving cable connected to computer USB port was the case. The WA tested 100R series to PB1 keeps injection current below maximum specification as MCU is powered off when JP1 strapped for OTG device provides +5 VBUS power to +3v3 LDO and MCU pin PB1.

    It would seem the USBv2 specification for VBUS signaling of PB1 supplied via OTG port device mode may have left out conditions leading to PB1 rail diodes being shorted in the process.
  • I am not sure what Amit was referring to. Is the damage to USBD+ and USBD- or to PB1? How is the USB being used, Host, device, OTG? Were the recommendations in SPMA056, section 4.3 the ones that were followed?
    www.ti.com/lit/an/spma056/spma056.pdf
  • Hi Linda,

    Since this discussion has been pulled offline, I am going to go ahead and close out this thread.