• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 30 subscribers
  • Views 531 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS570LS3137: MIBSPI Slave: Delay configuration in Mater

TMS570LS3137: MIBSPI Slave: Delay configuration in Mater

sreenivasan m
Genius 3705 points
Part Number: TMS570LS3137

Hi Team,

We are configuring TMS 570LS3137 controller in slave mode MIBSPI1. As per manual, we could see that enabling TGENA bit for every transfer is not required as it is in slave mode.
Can you please confirm on this. The reason is, when stop enabling TGENA bit (irrespective of enabling this, its value is always 1 in TGxCTRL register), we could see corrupted data is getting received on master end.
Can you please look into this?

Also, can you please provide us the details on all timing related configuration details we need to consider when we configure MIBSPI in slave mode?

Regards,
M.Sreenivasan.

  • 0
    TI__Guru**** 197126 points

    Hello,

    In slave mode, if the SPIENA is used, when the SPIDAT1 register is updated, the enable signal is released, and the transaction could begin. If the enable signal (SPIENA) is not used, the master should wait for 6 VBUSPCLK cycles before sending the clocks to begin the transaction. 

  • 0 in reply to QJ Wang
    Genius 3705 points
    Hi Wang,

    Can you answer for TGENA enabling part as well? Meanwhile we will check and come back on this.

    Regards,
    M.Sreenivasan.
  • 0 in reply to sreenivasan m
    TI__Guru**** 197126 points
    When operating in slave mode, the MibSPI uses the nCS to generate a trigger to the TG. If TG is enabled, the multi-buffer reads the current buffer of the TG and writes it into SPIDAT1. If Transfer Group is disabled, the multi-buffer does not update the SPIDAT1 register.

    If the selected TG is disabled and no update of the SPIDAT1 has been done, the data to be transferred is meaningless. Even the received data will not be copied to the multi-buffer RAM. However it will be available on SPIBUF register until it is overwritten by the subsequent receive data.