This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/TMDSRM48HDK: RM48HDK - External Memory Interface - TRM question

Part Number: TMDSRM48HDK
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

Hello community,

I am having some common understanding problems regarding the EMIF when I read the technical reference manual. According to the technical reference manual, it says that there are different sources which can generate requests for the EMIF. In that special case I am referring to the Direct Memory Access Controller. However, according to the TRM I don't see any request line connected to the EMIF when I read the chapter for the DMA component. I don't understand the difference between a HW and SW request and its outcome during the implementation. All examples I have seen so far are using HW requests e.g. Mibspi, SCI, etc...

My questions are:

  • Does it make sense to use the DMA controller when trying to read/write from the external memory device since there is no request line according to the TRM?
  • What is the benefit by using the DMA controller when data is read? (In general I know the capability of that module for the independent data transfer without CPU interception. But according to me, the C implementation for the emif will use pointers which will access the corresponding memory region to read/write data (which has to be set explicitly in the application). I don't see how the DMA controller can provide you an advantage to process the data independently since the application software will request it.
  • Assuming the emif is used during runtime, some activity on the emif pins should be seen according to my understanding (in case of an appropriate initialization e.g. MPU,Pinmux, data alignment, pointer usage, etc..)
  • Because of the internal timing paths for several device families some degradation regarding performance can be expected.
  • So the CPU will just stall and wait till the pipeline is filled for further processing when data is called/written?
  • Do you have an example for the emif and the dma to elaborate a little bit?

Thanks

  • Hello Mux,

    1. You can use DAM to access (read/write) the external memory through the EMIF interface
    2. DMA provides CPU independent data transfer between different memory locations, for example between SDRAM and DCAN RAM or ibSPI RAM). Please refer to the TRM
    3. Yes, EMIF pins toggle when there is EMIF activity (EMIF read or write).
    4. EMIF clock is much slower than CPU clock. Reading the EMIF data takes much longer than reading the data from the internal SRAM.
    5. What kind of example? example for transfer data from SDRAM to internal RAM, or from SDRAM to peripheral RAM?
  • HalCoGen has an example for MibSPI + DMA. This is used to transfer data between SRAM and MibSPI RAM. You can change the address to a location in SDRAM.