TMS570LC4357: Need explanation of GPIO[A|B] DMAREQ timing.

Your answer is a little  ambiguous, since the latter part can be interpreted as the DMA controller will only react to a second DMAREQ after the last element of a frame has been read. In this state, there will be contents in the DMA FIFO waiting to be written out, so the DMA transfer is not complete.

We have an FPGA on the EMIF which needs DMA support.

The natural way to implement DMA would be to have the peripheral assert the DMAREQ when service is needed.

When the peripheral detects an access to an adress within an address range, the DMAREQ should be deasserted.

Since our frame is at least 16 elements, deasserting DMAREQ after the first DMA read will ensure that it is not asserted at the end of the  last DMA  read transfer.

Can you confirm whether our idea will work or not?

A second problem popped up.

We want to transfer multiple frames with one frame per DMAREQ.

After transferring a full block, we plan to either reprogram the DMA Initial destination adress or enable another DMA channel in the BTC interrupt.

What happens if the  DMA channel had transferred a full block, and a new DMAREQ occurs before the BTC interrupt routine runs.

Hello Ulf,

Your idea works. The request is latched on HCLK rising edge, and should stay high for at least 1 HCLK cycle.

The whole block has been transferred, but has not completed, so the DMA status bit for this channel is still set. The new request will be in pending, bit in PEND register for this channel will be set.

That is again ambiguous.

I want to assert DMAREQ, and keep DMAREQ active until the FPGA is accessed.

When the FPGA  is accessed, it should deassert the DMAREQ signal.

The DMA controller should only transfer one frame.

If the pending register is set due to this, then I believe this will cause the transfer of two frames.

If the DMAREQ is asserted for two clocks, does that mean that two transfers will occur?

I also need a reply on what happens if a DMA channel has completed transferring all frames of a block, and takes BTC interrupt,

but the next DMAREQ comes before the DMA channel has been reinitialized.

Any news on this?

Hi Ulf,

I want to assert DMAREQ, and keep DMAREQ active until the FPGA is accessed.
QJW> This is OK. The DMAREQ can keep active as long as you can.

When the FPGA is accessed, it should deassert the DMAREQ signal.

The DMA controller should only transfer one frame.
QJW>yes, it should transfer only 1 frame for 1 DMAREQ

If the pending register is set due to this, then I believe this will cause the transfer of two frames.
QJW> When a HW request is generated and the channel is enabled, the corresponding bit "CHANNEL PENDING Register (PEND)" is set. The PEND bit is cleared at the end of a frame. This will not cause the transfer of two frames.

If the DMAREQ is asserted for two clocks, does that mean that two transfers will occur?
QJW>No, since it is triggered (rising edge if the polarity is HIGH) once.

I also need a reply on what happens if a DMA channel has completed transferring all frames of a block, and takes BTC interrupt,
but the next DMAREQ comes before the DMA channel has been reinitialized.
QJW>After the last transfer has completed. The new DMAREQ will set the PEND bit. But the pend bit will be cleared when control packet is modified.

Please let me know if my answer is not clear. Thanks

OK: This is how I interpret the functionality.
When the CPU H/W DMAREQ is activated, the pending bit is set, and a DMA transfer is started if a DMA is enabled
The DMAREQ signal can be Active without causing a second frame to be transmitted until the Pending bit is cleared at the end of the frame.

If the DMAREQ signal has been deactivated before the pending bit is clear, the DMA starts waiting for the next DMAREQ
If the DMAREQ signal has not been deactivated before the pending bit is clear, a new transfer is started.

* Can You confirm that this is how it works?
=====================
* This is how I suspect the DMA works: Can you confirm each item.

* Queued DMA transfers?
Once a DMAREQ has been activated and a transfer started:
If the DMAREQ is deactivated before the pending bit is cleared for the current transfer,
but is activated again before the pending bit has been cleared, a new request will be

* Pending Register clearing?
The pending register is cleared after the DMA has read the last Word of a frame from the source.
This and a few previous words may be in the DMA FIFO, waiting to be written out at this point of time.

=====================
My application will DMA from the source into two buffers each containing one block.
To avoid overhead, my plan is to use two DMA channels, each handling one buffer.
They will share the same DMAREQ signal, but only one will be active at a time.
The plan is to use the Block Transfer Complete Interrupt to switch between DMA channels.

Assume channel #1 is used for Block 1, channel #2 is used for Block 2.

DMA Channel 1.Block Transfer Complete Interrupt
Enable DMA #2

DMA Channel 2.Block Transfer Complete Interrupt:
Enable DMA #1

===================================================
At initialization I will write the Control packet to both DMA channels.
Both will be initialized to use the same DMAREQ signal
Then I will enable DMA Channel #1, but not DMA channel #2.

* Will the DMA #2 pending bit be set, when DMAREQ is activated, even though it is not enabled?

I know that if a DMA channel is enabled, and a DMAREQ is activated the pending bit will be set
and remain set, even if I disable the DMA channel.

If the DMA # pending bit is not set on DMAREQ when the channel is inactive:

* What happens if the DMAREQ is Active, and the DMA channel is enabled?
Will that set the pending bit and a transfer is performed?

Some notice what is not possible found on TI documentation:
When external DMAREQ signal is active before corresponding HWCHENA* bit, DMA controller silently ignore this request.
See e2e.ti.com/.../467894

Hello Jiri,

* Queued DMA transfers?
Once a DMAREQ has been activated and a transfer started:
If the DMAREQ is deactivated before the pending bit is cleared for the current transfer,
but is activated again before the pending bit has been cleared, a new request will be

QJW> DMA has a two level buffers to capture HW requests and one level of buffer to capture SW requests. If the pending request is not completely serviced by DMA and a HW request is generated by a peripheral onto the same channel, DMA will capture and recognize this HW request into its request buffer (2nd level buffer). DMA can not recognize two SW requests onto the same channel if the first SW request is still pending. So the SW request will be ignored.

* Pending Register clearing?
The pending register is cleared after the DMA has read the last Word of a frame from the source.
This and a few previous words may be in the DMA FIFO, waiting to be written out at this point of time.

QJW> The pending bit is cleared at the end of a transfer. A complete transfer means that all elements associated with a channel are completely transferred from its source to its destination.

Hello,

If a channel inside HWCHENAS is not enabled and a hardware request mapped to that channel is asserted, the hardware request will still be
captured inside CHANNEL PENDING Register (PEND).