TMS570LS3137: TMS570LS3137 MIBSPI slave in Multi-buffer Configuration

Hello Kalyan,

On thread title you are referring to TMS570LS3137 but the "spnu563a.pdf" is for TMS570LC4357...

1. Once we fill MIBSPI RAM (transmit buffer) with the required data and enable transfer group, we see transfer group enable field is always set to one. is this expected behaviour?

--> TGENA bit ( TGxCTRL[31] ) enables TG for transmit. If TGENA is cleared then trigger event will not start the transfer;
--> When TRIGGER EVENT is set to always then setting TGENA bit will trigger the transfer group;
--> If ONESHOTx bit ( TGxCTRL[30] ) is set then TGENA bit will be cleared after transfer is finished.
--> If ONESHOT bit is cleared then TGENA will remain set - I think this is your case.


2. once we fill MIBSPI RAM (transmit buffer) with required data and enabled transfer group and immediately before completion of the transfer can we copy another data to MIBSPI RAM (transmit buffer). if so which data will get transferred. please help me in understanding the behaviour in this case in detail.

--> Please take a look at the following thread:
e2e.ti.com/.../172572


Best regards,
Miro

Hi Miro,

Thanks for your quick response.

we have TMS570LS3137 MibSPI configured as slave and as per below screenshot from (spnu217b) one shot field is not required to configure in slave mode. i see TGENA bit always set even after the transmission is this expected behaviour?

Regarding my second question:

2. once we fill MIBSPI RAM (transmit buffer) with required data and enabled transfer group and immediately before completion of the transfer can we copy another data to MIBSPI RAM (transmit buffer). if so which data will get transferred. please help me in understanding the behaviour in this case in detail.

--> Please take a look at the following thread:
e2e.ti.com/.../172572

I referred the thread shared. actually my question is can we set MibSPI transmit buffer RAM back to back using "mibspiSetData" function generated by HALCOGEN tool, if so which data set will get transferred?

Thanks,

Kalyan

Hello Kalyan,
1. In Slave mode TGENA bit will remain set!

2. My understanding is that you should not use MiBSPI in that way. There will be a race between CPU and FSM.

Best regards,
Miro

Hi Miro,

Thanks for the info.

Related to my second question, below is exact steps we have in my code:
1. Set MibSPI Tx data using "mibspiSetData".
2. Enable TGENA bit for transmission.
3. Set MibSPI Tx data using "mibspiSetData". (Not sure by this time previously set of data is sent)
4. Enable TGENA bit for transmission.

After above steps we are not observing "INTFLGRDY" field of TGINTFLG register is not set . is this expected in this case.

do you have any suggestion to handle this case?

Thanks,
Kalyan