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TMS570LC4357: DCAN FIFO: Design Exception DCAN#27

Ondrej Vaverka
Prodigy 70 points
Part Number: TMS570LC4357

Hello,

please provide a support. I am currently facing to the DCAN FIFO issue described by the document "SPNZ232B–August 2015–Revised June 2018" and marked as DCAN#27. Correct order of CAN messages is absolutely critical for our application.
As I understood the described workaround: The RX FIFO can be still used, but IF2 should be just replaced by IF3 register. To make workaround more clear, is it necessary to use DMA for IF3 register set access? Is possible to configure DCAN to use RX FIFO and generate interrupt when IF3 is updated by message object from FIFO? I just want to avoid DMA usage. Please clarify this.

Thank you in advance.

  • 0
    TI__Mastermind 49120 points
    Hi Ondrej,

    I will look into this and get back to you as soon as possible.

    Regards,
    Sunil
  • 0
    TI__Mastermind 49120 points
    Hi Ondrej,

    It is not necessary to use the DMA request with IF3. You can also choose to generate an interrupt to the CPU once the message object is transferred to the IF3 registers so that the CPU can read the received message. Use of the DMA with IF3 allows you to buffer the FIFO data for the CPU.

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Genius 3315 points
    Hi Sunil,
    please may you clarify your answer in more detail - is it possible not to use the DMA in this data chain (as Ondrej mentioned "to avoid the DMA use")?
    In other words, is is a sufficient ("standalone") solution just to replace the IF2 register by the IF3 one? I think so - based on your sentence "It is not necessary to use the DMA request with IF3" - anyway may you confirm this conclusion?

    Data buffering is performed by the RX FIFO. Of course, there can be utilize an additional buffering (just limited by available RAM space ;-)) on the higher level by using the DMA for IF3 reading.

    Thanks a lot,
    Best regards, Jiri
  • 0 in reply to Jiri Janacek
    TI__Mastermind 49120 points
    Hi Jiri,

    Yes, you can configure the IF3 register set to automatically update when a message is received and then generate an interrupt to the CPU to process the received message.

    Please note that IF3 can only be used for receiving frames.

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Prodigy 70 points
    Hi Sunil,
    thank you for your answer. I did few tests with this configuration: DCAN RX FIFO enabled, message reading by IF3 set, IF3 update interrupt enabled. The IF3update interrupt sets flag, which triggers process with IF3 reading procedure. The issue DCAN#27 is still observed even with this configuration.
    So... It seems that the problem is in the FIFO itself, not in the access method.

    Could you confirm my opinion and suggest another solution?