TM4C1231E6PM: Tiva C PF0 NMI feature,

Hello Paddu,

Both statements are accurate. The operative word in the first statement is *function*. That doesn't mean it's been configured, just that it can function as a GPIO. Maybe more DS info can help here.

First off, more info about NMI:

"The NMI signal is an alternate function for either GPIO port pin PD7 or PF0. The alternate function
must be enabled in the GPIO for the signal to be used as an interrupt, as described in
“General-Purpose Input/Outputs (GPIOs)” on page 613. Note that enabling the NMI alternate function
requires the use of the GPIO lock and commit function just like the GPIO port pins associated with
JTAG/SWD functionality, see page 649."

Now then, the GPIOCR register is for GPIO commit. Further information about it is:

"This register is designed to prevent accidental programming of the registers that control
connectivity to the NMI and JTAG/SWD debug hardware. By initializing the bits of the
GPIOCR register to 0 for the NMI and JTAG/SWD pins (see “Signal Tables” on page 1075
for pin numbers), the NMI and JTAG/SWD debug port can only be converted to GPIOs
through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the corresponding
registers.
Because this protection is currently only implemented on the NMI and JTAG/SWD pins
(see “Signal Tables” on page 1075 for pin numbers), all of the other bits in the GPIOCR
registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it
is always possible to commit new values to the GPIOAFSEL, GPIOPUR, GPIOPDR,
or GPIODEN register bits of these other pins."

The intent here is to prevent a user from accidentally programming the various GPIO functionality that is available without intentionally using the commit functionality.

So while the NMI can *function* as a GPIO after reset, it isn't *configured* as a GPIO, and configuration is controlled by having the NMI protected by GPIOCR so configuration can only occur when GPIO commit is used beforehand.