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Original question:

TMS570LS3137: TMS570LS3137 checkRAMECC double bit error verification

TMS570LS3137: TMS570LS3137: pbistSelfCheck method details

Kalyan Vagvala61
Expert 1075 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hi,

We are using HALCOGEN generated code for performing built-in test using PBIST controller. I could see below comment for pbistSelfCheck() method. I would like to know the registers that are used in the function pbistSelfCheck() function that are not listed in TRM. Could you please share those details?

/** @fn void pbistSelfCheck(void)
* @brief PBIST self test Driver
*
* This function is called to perform PBIST self test.
*
* @note This Function uses register's which are not exposed to users through
* TRM , to run custom algorithm to make PBIST Fail. Users can use this function as Black box.
*
*/

Thanks,

Kalyan

  • 0
    TI__Guru**** 196226 points

    Hello Kalyan,

    pbistSelfCheck() generated by HALCoGen uses custom algorithm which will make the PBIST fail to ensure that PBIST is capable of detecting and indicating a memory self-test failure. The reserved register (pbistREG->rsvd1[1U]  = 1U;) is to run the custom algorithm. The custom algorithm is defined by the lines just above the line "pbistREG->rsvd1[1U]    = 1U";

    We do not want customers to write to the "RSVD" registers because there is lot of chances for user to make error with custom algo and make the device memory test to produce erroneous result. 

    You could also do pbist Self Check by simply choosing wrong memory against wrong algorithm. i.e you can select a single port Memory and choose a dual port Test algorithm ( basically not follow PBIST RAM Grouping Table in datasheet). I will modify the code for you as reference.

  • 0 in reply to QJ Wang
    TI__Guru**** 196226 points

    I modified the code, and can get an expected error.

    /* CPU control of PBIST */

    // pbistREG->DLR = 0x10U;

    /* Custom always fail algo, this will not use the ROM and just set a fail */

    /*

    pbistREG->RAMT = 0x00002000U;

    *(volatile uint32 *)0xFFFFE400U = 0x4C000001U;

    *(volatile uint32 *)0xFFFFE440U = 0x00000075U;

    *(volatile uint32 *)0xFFFFE404U = 0x4C000002U;

    *(volatile uint32 *)0xFFFFE444U = 0x00000075U;

    *(volatile uint32 *)0xFFFFE408U = 0x4C000003U;

    *(volatile uint32 *)0xFFFFE448U = 0x00000075U;

    *(volatile uint32 *)0xFFFFE40CU = 0x4C000004U;

    *(volatile uint32 *)0xFFFFE44CU = 0x00000075U;

    *(volatile uint32 *)0xFFFFE410U = 0x4C000005U;

    *(volatile uint32 *)0xFFFFE450U = 0x00000075U;

    *(volatile uint32 *)0xFFFFE414U = 0x4C000006U;

    *(volatile uint32 *)0xFFFFE454U = 0x00000075U;

    *(volatile uint32 *)0xFFFFE418U = 0x00000000U;

    *(volatile uint32 *)0xFFFFE458U = 0x00000001U;

    */

    /* PBIST_RUN */

    // pbistREG->rsvd1[1U] = 1U;

    /* Select all algorithms to be tested */

    pbistREG->ALGO = 0x00000002; //Algorithm 4

    /* Select RAM groups */

    pbistREG->RINFOL = 0x1 << (7-1); //MibSPI1 RAM

    /* Select all RAM groups */

    pbistREG->RINFOU = 0x00000000U;

    /* ROM contents will not override RINFOx settings */

    pbistREG->OVER = 0x0U;

    /* Algorithm code is loaded from ROM */

    pbistREG->ROM = 0x3U;

    /* Start PBIST */

    pbistREG->DLR = 0x14U;

    The code uses algorithm #2 (triple_read_fast_read) to test MibSPI1 RAM. The algorithm #2 is designed for ROM.