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Original question:

TMS570LS3137: ADC#1:ERRATA SPNZ195G

TMS570LS3137:

Midhun M
Prodigy 230 points
Part Number: TMS570LS3137

Hi, 

As a continuation of the thread :https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/765766

The question is regarding the errata "The errata spnz195G for "TMS570LS3137"
: "An offset error is introduced in the conversion result of any channel if a current is being injected into a shared input channel." , if the input voltage on a shared input ADC channel > VCCAD-0.3V and if there is an overlap for sampling windows of two ADCs."

1. The ADC configuration used is as below: ADC sampling frequency is 104.9869 KHz. ADC1 Group-1 and ADC2 Group-2 are not triggered simultaneously. ADC1 Group-1 gets triggered  first and subsequently ADC2 Group-1 is triggered with approx.., 4 cycles delay. (ie. 4 * 1/160MHz = 0.025 uS).

In this case will there be an offset error?

2. The ADC inputs are driven with instrumentation amplifier AD8421, followed by RC filter (100ohm, 1nF). From the datasheet the maximum bias current is mentioned for IAOSB1=14uA and IAOSB@=12uA. 

Can we calculate the maximum offset voltage at ADC1 in case of input at ADC2 > 4.7V as (14+12)uA x 100 =260uV ?

Thanks

Midhun.

  • 0
    TI__Mastermind 49120 points
    Hi Midhun,

    See comments below:

    1. The ADC configuration used is as below: ADC sampling frequency is 104.9869 KHz. ADC1 Group-1 and ADC2 Group-2 are not triggered simultaneously. ADC1 Group-1 gets triggered first and subsequently ADC2 Group-1 is triggered with approx.., 4 cycles delay. (ie. 4 * 1/160MHz = 0.025 uS).

    In this case will there be an offset error?

    >> Assuming that the sampling periods are longer than 4 cycles, there will still be an overlap of the sampling periods which will cause an offset error in the conversions.

    2. The ADC inputs are driven with instrumentation amplifier AD8421, followed by RC filter (100ohm, 1nF). From the datasheet the maximum bias current is mentioned for IAOSB1=14uA and IAOSB@=12uA.

    Can we calculate the maximum offset voltage at ADC1 in case of input at ADC2 > 4.7V as (14+12)uA x 100 =260uV ?

    >> You need to also include the ON resistances of the "closed" switches on the path.
  • 0 in reply to Sunil Oak
    Prodigy 230 points

    Hi Sunil,

    Thanks for clarification

    Hence considering the internal on resistance of the ADC and the external resistor 

    Rmux(ADC2)+Rsamp+Rmux(ADC1)+REXT = 250 + 250 + 250 +100= 850ohm

    Can we consider the maximum offset voltage as 850ohm x (14+12)uA = 22.1mV corresponding to 18bit error?

    Regards,

    Midhun

  • 0 in reply to Midhun M
    TI__Mastermind 49120 points

    Hi Midhun,

    Yes, that's correct.

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Prodigy 230 points

    Thank you Sunil