TMS570LS3137: Timing requirement details

sreenivasan m

Hi Team,

https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/798398 as part of this case, could see we need to wait 128 VCLK cycles for MibSPI each buffer initialization completion.

Can we have documentation for this to refer?

over 6 years ago

0 Sunil Oak over 6 years ago

TI__Mastermind 49120 points

Hello,

The memory initialization takes one VCLK cycle per row for each of the memories that support auto-initialization. This information is missing from the TRM, and would be added in the next update.

Regards,

Sunil

0 sreenivasan m over 6 years ago in reply to Sunil Oak

Genius 3705 points

Thank you, please provide us the version of the TRM document which we can refer for future. Also, please include self test timing details as well.

0 Sunil Oak over 6 years ago in reply to sreenivasan m

TI__Mastermind 49120 points

The next version of the TRM would be SPNU499D.

Regards,

Sunil

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TMS570LS3137: Timing requirement details