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DCAN IF1CMD, DCAN IF2CMD Register Busy Bit setting condition

Pashan
Intellectual 715 points
Other Parts Discussed in Thread: HALCOGEN

Hello,

Within DCAN there are registers called

IF1CMD, IF2CMD

Within those registers, there is a bit called BUSY.

This above mentioned bit is set to 1 whenever CPU writes the MESSAGE NUMBER field of the above registers.

Is that the one and only one condition due to which this BUSY bit will be set to 1 or there are more than one condition due to which this bit have the possibility to set to 1?

Please help.

Thank you.

Regards

Pashan

 

  • 0
    TI__Mastermind 49120 points

    Hello,

    The BUSY bit get set whenever the application writes to the MESSAGE NUMBER field of the respective IF1CMD or IF2CMD registers. This bit gets cleared only after the transfer between the interface register and the message RAM is completed.

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Prodigy 185 points

    Hi,

    In halcogen code busy bit is checked in a while loop. Is there a case in which the busy bit is not cleared at all? Or is these guaranteed by microcontroller's hardware?

    Regards,

    Fabian

  • 0 in reply to Fabian Nenniger1
    TI__Mastermind 49120 points

    Hi Fabian,

    Sorry for the long delay. The BUSY bit is cleared in hardware as explained in the TRM.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Prodigy 40 points

    Hi everyone, 

        I have a question about that: I generated a CAN driver with Halcogen 2.09. When I call dcanInit() it gets stucked waiting for the busy bit clearing forever and ever. The first busy loop generated in dcan.c is the following:

    while ( (dcanREG1->IF1STAT & 0x80) == 0 )
    {
    }

    Is it valid? Shouldn't that be != 0 ? In the HalcoGen help there's an implementation that does as I believe:

    while (canREG1->IF1STAT & 0x80);

    Is this a bug in Halcogen? I will appreciate your help, thanks in advance!

    Emanuel.