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RTOS/TM4C1294NCPDT: Mailbox behavior in TI-RTOS multi-threaded (pre-emptive threads) application

Part Number: TM4C1294NCPDT

Tool/software: TI-RTOS

Hi,

I would like to know about mailbox behavior in TI-RTOS multi threaded application.

Consider application has tasks and ISRs as below:

Note: Higher the number, higher the priority.

T1 // Priority 1
{
Mailbox_pend(mbox_handle, buffer, BIOS_WAIT_FOREVER);
}

T2 // Priority 2
{
Mailbox_post(mbox_handle, buffer, BIOS_WAIT_FOREVER);
}

T3 // Priority 3
{
Mailbox_post(mbox_handle, buffer, BIOS_WAIT_FOREVER);
}

ISR1 // Priority highest among all tasks
{
Mailbox_post(mbox_handle, buffer, BIOS_WAIT_FOREVER);
}

ISR2 // Priority highest among all tasks
{
Mailbox_post(mbox_handle, buffer, BIOS_NO_WAIT);
}

Case 1: Suppose if T2 is running and Mailbox_post() is executing.
What will happen if T3 is scheduled to run ? T3 will be in execution or T2 continue Mailbox_post() or anything else ?

Case 2: Suppose if T2 is running and Mailbox_post() is executing.
What will happen if ISR1 is scheduled to run because of hardware interrupt ? ISR1 will be in execution or T2 continue Mailbox_post() or anything else ?

Case 3: Suppose if T2 is running and Mailbox_post() is executing.
What will happen if ISR2 is scheduled to run because of hardware interrupt ? ISR2 will be in execution or T2 continue Mailbox_post() or anything else ?

What will be behavior in above cases ?

  • Hi Harshel,

      I think you are already asking the same question in another post https://e2e.ti.com/support/microcontrollers/other/f/908/p/823253/3046833#3046833. Rob will be able to assist you there. 

  • Harshel said:
    Case 1: Suppose if T2 is running and Mailbox_post() is executing.
    What will happen if T3 is scheduled to run ? T3 will be in execution or T2 continue Mailbox_post() or anything else ?

    You show task code that, taken literally, performs one Mailbox operation and then finishes, so I don't really understand the situation.  Are you meaning to show tasks that repeatedly call the Mailbox operation in a loop?

    If T2 is in the middle of a Mailbox_post() when T3 is scheduled to run, it depends where T2 is inside Mailbox_post().  Mailbox operations contain a "critical section" where the Task scheduler is disabled.  If T3 becomes ready when T2 is in that critical section then T3 will be held off until T2's Mailbox_post() exits the critical section, at which point T3 will preempt T2 and start running.  When T3 calls Mailbox_post(), it will either succeed because there are available free message slots, or it will block because there are no more free message slots.

    Once the Mailbox becomes full and there are no more free message slots, T1 will get to run and will free one Mailbox message slot.

    Harshel said:
    Case 2: Suppose if T2 is running and Mailbox_post() is executing.
    What will happen if ISR1 is scheduled to run because of hardware interrupt ? ISR1 will be in execution or T2 continue Mailbox_post() or anything else ?

    First, please note that you can't use BIOS_WAIT_FOREVER in an ISR, as ISR1 is doing (ISR2 is correct with BIOS_NO_WAIT).

    The ISR will preempt T2 and attempt to post the Mailbox.  If there are free slots available then it will succeed and return TRUE.  If there are no free slots available then it will fail to post the message and will return FALSE.

    Harshel said:
    Case 3: Suppose if T2 is running and Mailbox_post() is executing.
    What will happen if ISR2 is scheduled to run because of hardware interrupt ? ISR2 will be in execution or T2 continue Mailbox_post() or anything else ?

    This is the same as Case 2, I don't understand what difference you're trying to inquire about.

    A lot depends on how many message slots are available in the Mailbox, and how the ISRs and tasks are scheduled.

    You will need to post more complete sample scenarios for me to be able to provide a better answer.

    Regards,

    - Rob

  • Purpose is to confirm whether Mailbox_post() is in or out of critical section, after preemption by any high priority task or ISR should be successful for Mailbox_post() if free message slots are available.

  • OK, then I assume I've answered your questions sufficiently.  Please restate the question(s) if I have not answered sufficiently.

    Regards,

    - Rob

  • Hi Rob,

    I understood task synchronization while executing mailbox critical section.

    If mailbox (e.g. M1) is executing critical section because of POST(M1) from task T1 or PEND(M1) in task T2 and now ISR is invoked. From that ISR, we plan to do POST(M1). Will this situation be handled correctly?

    Thanks & Regards

    Abhijit