Hi Team,
During our internal testing, where EMIF is configured to use CE2CFG with proper write and read cycle timings and no memory is connected to EMIF.
We could tried to perform read and write operations for the configured memory region specified by CS2 as per TRM.
Could see clock signals for CS for write is working (mean, we are able to see assertion and disassertion), but this is not happening in case of read signal.
Can you please check and let us know is it expected behavior? If not, can you help us for further way forward to look forwards?
