TMS570LC4357: F021 Flash Bootloader Proper Usage

Chris Yorkey

Genius 15305 points

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

TI Hercules Friends & Family,

Our customer would appreciate some input regarding F021 Flash usage.

They are having some difficulty getting the F021 library to work from RAM.

The HL_sys_link.cmd file seems to be configuring memory correctly;

In addition they tried setting RAM permissions to RWX (and MPU region in HALCoGen to allow execution); it did not help.

They also tried the compiler option --ramfunc and using the .TI.ramfunc align(32) to automatically copy the library during initialization; see commented out line in the USER CODE section.

When the code is running as soon as the following line is reached a prefetchEntry interrupt fires;

fapi_status = Fapi_initializeFlashBanks( SYS_CLK_FREQ );

I have included a screenshot from them below. Unless we are understanding the LR register wrong, it seems the fault originates at an address outside of the defined memory region (0x08080004)?

Another thing noticed is the RAM ECC region doesn’t seem to be initialized? This obviously doesn't seem normal.

Suggestions welcomed.

TY,
CY

/*----------------------------------------------------------------------------*/

/* Memory Map */

MEMORY

{

/* USER CODE BEGIN (2) */

/* USER CODE END */

VECTORS (X) : origin=0x00000000 length=0x00000020

FLASH0 (RX) : origin=0x00000020 length=0x001FFFE0

FLASH1 (RX) : origin=0x00200000 length=0x00200000

STACKS (RW) : origin=0x08000000 length=0x00001500

RAM (RW) : origin=0x08001500 length=0x0007eb00

/* USER CODE BEGIN (3) */

//RAMFUNC (RWX): origin=0x08070000 length=0x00010000

/* USER CODE END */

}

/* USER CODE BEGIN (4) */

/* USER CODE END */

/*----------------------------------------------------------------------------*/

/* Section Configuration */

SECTIONS

{

/* USER CODE BEGIN (5) */

/* USER CODE END */

.intvecs : {} > VECTORS

.text align(32) : {} > FLASH0 | FLASH1

.const align(32) : {} > FLASH0 | FLASH1

.cinit align(32) : {} > FLASH0 | FLASH1

.pinit align(32) : {} > FLASH0 | FLASH1

.bss : {} > RAM

.data : {} > RAM

.sysmem : {} > RAM

FEE_TEXT_SECTION : {} > FLASH0 | FLASH1

FEE_CONST_SECTION : {} > FLASH0 | FLASH1

FEE_DATA_SECTION : {} > RAM

/* USER CODE BEGIN (6) */

.flashapi : load = FLASH0, run = RAM, LOAD_START(FlashApi_LoadStart), LOAD_END(FlashApi_LoadEnd), LOAD_SIZE(FlashApi_LoadSize), RUN_START(FlashApi_RunStart), RUN_END(FlashApi_RunEnd), RUN_SIZE(FlashApi_RunSize),

{

--library= "C:\ti\Hercules\F021 Flash API\02.01.01\F021_API_CortexR4_BE_L2FMC_V3D16.lib" (.text)

"C:\ti_workspace\iVM_Bootloader\Debug\source\Fapi_UserDefinedFunctions.obj" (.text)

}

// .TI.ramfunc align(32) : { "C:\ti\Hercules\F021 Flash API\02.01.01\F021_API_CortexR4_BE_L2FMC_V3D16.lib" (.text) } load=FLASH0, run=RAMFUNC, table(BINIT)

/* USER CODE END */

}

over 5 years ago

0 dzhou over 5 years ago

TI__Genius 9065 points

Hello Chris,

You are having a Prefetch abort. What is the CPSR register value?

The F021 Flash API routines must be run in a privileged mode to allow access to the Flash memory controller registers.

best regards,

David Zhou

0 Chris Yorkey over 5 years ago in reply to dzhou

TI__Genius 15305 points

Hello David,

The CPSR register value was 0x397 (see screenshot).

The Flash functions were working fine until they apparently moved the library to RAM.

Any other words of wisdom you can share would be greatly appreciated!

TY,
Chris

0 dzhou over 5 years ago in reply to Chris Yorkey

TI__Genius 9065 points

Chris,

We have bootloader examples available here:

http://git.ti.com/hercules_examples/hercules_examples/trees/master/Bootloaders

The bootloader copies the F021 Flash API to RAM and execute APIs from RAM instead of Flash.

Please also take a look at below E2E thread which is relevant:

https://e2e.ti.com/support/microcontrollers/hercules/f/312/p/794262/2938629?tisearch=e2e-sitesearch&keymatch=flash%20api#2938629

best regards,

David Zhou

0 Chris Yorkey over 5 years ago in reply to dzhou

TI__Genius 15305 points

David,

Thanks so much!

Interestingly, I don't see source available at the git link?

Can you comment?

TY,

Chris

0 dzhou over 5 years ago in reply to Chris Yorkey

TI__Genius 9065 points

Chris,

Source code is there.

http://git.ti.com/hercules_examples/hercules_examples/trees/master/Bootloaders/SafetyMCU_Bootloaders/source

and bl_flash.c is calling Flash API functions.

There is command file for each device, e.g.:

http://git.ti.com/hercules_examples/hercules_examples/trees/master/Bootloaders/SafetyMCU_Bootloaders/TMS570LC43x

The file is bl_link.cmd.

best regards,

David Zhou

0 dzhou over 5 years ago in reply to dzhou

TI__Genius 9065 points

Chris,

I would like to point out the copy is done in the main function of bl_main,c:

void main(void)

{

g_pulUpdateSuccess[3] = 0x30002019; /*version number, 03.00, in 2019*/

uint32_t fnRetValue = 0;

/* Initialize SCI Routines to receive Command and transmit data */

sciInit();

/* Copy the flash APIs to SRAM*/

//_copyAPI2RAM_(&apiLoadStart, &apiRunStart, &apiLoadSize);

memcpy(&apiRunStart, &apiLoadStart, (uint32)&apiLoadSize);

Customer would need to do something similar for their application.

best regards,

David Zhou

0 Chris Yorkey over 5 years ago in reply to dzhou

TI__Genius 15305 points

Thank you David.

Appreciate the extra pointers and comments.

I think this will help a lot. Stay tuned.

Regards,

Chris

0 Chris Yorkey over 5 years ago in reply to Chris Yorkey

TI__Genius 15305 points

David,

I want to again thank you for your input. Quite helpful.

At this point in time, the code looks like a good reference for the customer; I believe their main issue at this point is related to permissions and/or ECC, etc.

No further actions at this point but I will update the thread if something short-term comes back. Otherwise, we will close it out.

TY,
Chris

0 Chris Yorkey over 5 years ago in reply to Chris Yorkey

TI__Genius 15305 points

David,

Again, thanks for your help. It appears the cache setting for the SRAM memory region might have been the main culprit.

At this point the customer's F021 routines are successfully executing from SRAM. They can read and erase/write to Flash memory with one caveat;

Now they're encountering an interrupt vector fault when attempting an erase of a sector in Flash Bank 0. Probably some sort of user configuration/setup issue. Again no further actions required on your end from this thread's perspective. I’ll keep you posted if otherwise.

Regards,
Chris

0 dzhou over 5 years ago in reply to Chris Yorkey

TI__Genius 9065 points

Chris,

Thanks for the update.

Just FYI: The interrupts are not disabled inside the flash APIs. It is recommended that customers disable the interrupts before calling flash API.

best regards,

David Zhou

0 Chris Yorkey over 5 years ago in reply to dzhou

TI__Genius 15305 points

Thanks again David,

Understood. The converse of that is that Users can have interrupts enabled during this Erase process as the API supports that. I am also asking where their code that performs the Flash operation is, specifically, since if the code is also located in Sector 0, that would be a problem as you can’t erase that area. Also, I'm asking where is the interrupt vector located (0x00-0x20?) and if they can try to Erase another Sector (such as 4) only to see if that shows different behavior.

TY,
Chris

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TMS570LC4357: F021 Flash Bootloader Proper Usage