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TM4C1290NCZAD: I2C Master Read-Access

Takayuki Miyazaki
Genius 10120 points
Part Number: TM4C1290NCZAD

Hello team,

 

Our customer is developing their system with TM4C1290NCZAD. TM4C1290 is configured as I2C Master(System clock :120MHz). Recently, customer noticed there were reflected signals which TM4C1290 drives on SCL-line during Read-access.I attached customer’s evaluation result (TM4C1290NCZAD_SCL.pptx).

Would you consider there is any issue for TM4C1290 by this SCL-falling-signal?

Also, customer wants to know how TM4C1290 latches Read-Data during Master read. In the case of TM4C1290 device, Is Read-data latched by voltage-high-Level? Or by SCL rise-clock-edge? Could you please clarify it, please?

Best regards,

Miyazaki

  • 0
    TI__Guru 72500 points

    The reflection on SCL will not be an issue to the TM4C acting as master, but may be perceived by the slave as an extra clock signal and cause an extra data shift while reading or writing. This depends on the I2C slave device's hysteresis or filter ability. Using a transmission line layout with no stubs with an AC termination at the end should help.

    The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low period. The actual position is affected by the value programmed into the TPR.

  • 0
    Guru 117855 points

    Takayuki Miyazaki said:
    ...there were reflected signals which TM4C1290 drives on SCL-line during Read-access.

    Were those same 'reflected signals' present when, 'Writing to the Slave - as well?'   (that's highly suspected)

    Along w/vendor's (transmission line) direction - the SCL's pcb trace should be as short & direct as possible - perhaps  widened  as well...

  • 0 in reply to Bob Crosby
    TI__Genius 10120 points

    Hi Bob,

    Thanks for clarification for this.

    Best regards, Miyazaki