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Original question:

nERROR pin and ESM Low-Time Counter Preload Register

TMS570LS3137: ESMLTCPR register details

sreenivasan m
Genius 3705 points
Part Number: TMS570LS3137

Hi Team,

Could see from the case - "https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/251397?tisearch=e2e-sitesearch&keymatch=ESMLTCPR" below details are missing in the TRM (spnu499c.pdf).

"The ESMLTCPR bit 15:14 are the only bits that you can change. Bit 13:0 is default to all 1's and these are read only bits.If you look at the TRM, the bit 15:14 is denoted as R/W while bit 13:0 denoted as R-1.  I agree that it is a little bit confusing, but it is actually all 1's."

The value to be configured is R-1 instead of R (VCLK cycles) is missing in specific. Can we have these details added in the document?

  • 0
    TI__Mastermind 49120 points

    Hi Sreenivasan,

    Are you looking at the latest updated TRM for TMS570LS3137? I have pasted below from SPNU499C updated in March 2018.

    The register bit-field default values are specified correctly above.

    Please note that you can use the "Submit Documentation Feedback" link at the bottom of each page to provide feedback on documentation issues. This brings up a form that you can use to fill out the necessary information for us to track down the issue and correct it in the next release, if required.

    Regards, Sunil