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Original question:

TMS570LS3137: cpuSelfTest Query

TMS570LS3137: TMS570LS3137: cpuSelfTest Query (Continuation)

sreenivasan m
Genius 3705 points
Part Number: TMS570LS3137

Hi Team,

This is regarding the continuation of the case : https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/823182?tisearch=e2e-sitesearch&keymatch=%25252525252520user%2525252525253A373270

Can you please conform for the below question:

"When i configure HCLK = 180 MHZ, VCLK = 90 MHZ, STCCLK = 90MHZ, stcREG->STCTPR = 0x0x8019UL (which is 364 usec as per TRM); cpuSelfTest() fails in this case. why is that what would be the good tolerance value?"

With the timeout value of 364 micro seconds, the test case fails, but with increase in timeout it works. Does it requires an update in the document or something we are missing in our tests?

  • 0
    TI__Mastermind 49120 points

    Sreenivasan,

    The STCTPR register configures the timeout period to be a fallback in case the CPU self-test run does not complete. This allows you to reset the CPU with a timeout and process the CPU self-test results. This timeout does not need to be exactly the number of VCLK cycles required for the full self-test.

    On TMS570LS3137 it takes 32760 cumulative STC clock cycles to run all 24 STC intervals. This is exactly 364 us at 90MHz. You need to define the timeout period which is larger than this time required. I would suggest configuring a timeout period to a value that your application can handle for the CPU to not be available while running the self-test.

    Regards, Sunil