CCS/TMS570LC4357: How to disable a cache for a perticular memory region

Tool/software: Code Composer Studio

Hi Team,

As per my application i have to enable the cache for a particular memory region and want to disable for some.

Is there any way that i can achieve it?

As halcogen provides this following code for enabling and disabling the cache:

_cacheEnable_

stmfd sp!, {r0-r1}
mov r0,#0

MRC p15, #0, r1, c1, c0, #1 ; Read auxiliary control register
BIC r1, r1, #0x1 << 5 ; bit is default set to disable ECC. Clearing bit 5
MCR p15, #0, r1, c1, c0, #1 ; enable ECC, generate abort on ECC errors, enable
; hardware recovery

MRC p15, #0, R1, c1, c0, #0 ; Read System Control Register configuration data
ORR R1, R1, #0x1 <<12 ; instruction cache enable
ORR R1, R1, #0x1 <<2 ; data cache enable
DSB
MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache
DSB ; delay is required, manually added
MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache
DSB ; delay is required, manually added
MCR p15, #0, R1, c1, c0, #0 ; enabled cache RAMs
ISB

ldmfd sp!, {r0-r1}

bx lr
.endasmfunc

and 

.def _cacheDisable_
.asmfunc

_cacheDisable_

stmfd sp!, {r1}

MRC p15, #0, R1, c1, c0, #0 ; Read System Control Register configuration data
BIC R1, R1, #0x1 <<12 ; instruction cache disable
BIC R1, R1, #0x1 <<2 ; data cache disable
DSB
MCR p15, #0, R1, c1, c0, #0 ; disabled cache RAMs
ISB

ldmfd sp!, {r1}

bx lr
.endasmfunc

so how can i make the cache type register to enable and disable it for a perticular region?

Please assist me in this case.

Regards,

Shivam Kakad