Tool/software: TI C/C++ Compiler
Hi,
I read this post https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/382385?tisearch=e2e-sitesearch&keymatch=scmcntrl
I have a follow on question to this post. The post says to clear parity error flags in DMA, L2FMC and L2RAMW. When I set SCMCNTRL to 0x0A050505 to start the transaction parity test, I do not see any parity error being set in L2FMC. I was expecting to see parity error being set on FEDAC_PASTATUS, FEDAC_PBSTATUS, L2FMCPOM_POMFLG registers, but they are all 0x0 in Code Composer. Is this expected?
Also, for L2RAMW, I only see RAMERRSTATUS CPEOI bit being set. Should I expect bit MSACP, PACE to be set too?
Thanks!
JC