Hello,
I am using TI's F021 API for erasing and writing to both bank 0 and bank 1.
The entire F021 API runs in RAM as well as my code calling it. The rest of my code runs in bank 0.
Erasing/Writing bank 1 works perfectly but when erasing/writing bank 0 I quite consistently (about 9 / 10 times) get a very confusing prefetch abort.
For details see: https://community.arm.com/developer/ip-products/processors/f/cortex-r-forum/44736/atcm-ecc-error-causes-prefetch-abort-despite-ecc-check-being-disabled
Two questions:
- Am I using the API incorrectly / Do I need to move more stuff into RAM?
- Where can I find more information on the FSM registers? The TRM (http://www.ti.com/lit/ug/spnu499c/spnu499c.pdf) only references two of them (FSM_WR_ENA, FSM_SECTOR) making it impossible for me to implement my own flash routines.