Tool/software: Code Composer Studio
I am currently working on the STC tests for CPU ARM core and for nHET module. For STC1 for ARM core test is ok and no problem. But for STC2 for nHET module, after I have called the routine for STC2, the program stuck at CPU idle state. Please refer to the following codes for STC2 configuration:
/* Configure the clock divider */
systemREG2->STCCLKDIV = ((uint32)(config->stcClockDiv & (uint32)0x07u) << 24u);
systemREG2->STCCLKDIV = ((uint32)(config->stcClockDiv & (uint32)0x07u) << 24u);
systemREG1->SYSESR = 0x20; // Clear CPU reset flag
/* Configure the interval count & restart/continue */
tempVal = 0U;
tempVal |= ((uint32)config->intervalCount << STC_STCGCR0_INTCOUNT_START);
if (TRUE == config->restartInterval0) {
tempVal |= STC_STCGCR0_RS_CNT;
}
tempVal = 0U;
tempVal |= ((uint32)config->intervalCount << STC_STCGCR0_INTCOUNT_START);
if (TRUE == config->restartInterval0) {
tempVal |= STC_STCGCR0_RS_CNT;
}
stcREG2->STCGCR0 = tempVal;
/* wait for 16 VBUS clock cycles at least, based on HCLK to VCLK ratio */
for (i=0U; i<(16U + (16U * 3U)); i++){ /* Wait */ }
for (i=0U; i<(16U + (16U * 3U)); i++){ /* Wait */ }
if (STC2_COMPARE_SELFCHECK == testType) {
/* If in compare selfcheck (fault injection) mode then setup STCSCSCR */
stcREG2->STCSCSCR = (uint32)(STC_STCSCSCR_FAULT_INS|STC_STCSCSCR_SELF_CHECK_KEY);
}
else if(STC2_RUN == testType) {
/* else disable selfcheck mode and return to normal BIST operation */
stcREG2->STCSCSCR = (uint32)(0x0U);
}
/* Setup the timeout value */
stcREG2->STCTPR = config->timeoutCounter;
/* If in compare selfcheck (fault injection) mode then setup STCSCSCR */
stcREG2->STCSCSCR = (uint32)(STC_STCSCSCR_FAULT_INS|STC_STCSCSCR_SELF_CHECK_KEY);
}
else if(STC2_RUN == testType) {
/* else disable selfcheck mode and return to normal BIST operation */
stcREG2->STCSCSCR = (uint32)(0x0U);
}
/* Setup the timeout value */
stcREG2->STCTPR = config->timeoutCounter;
/* Segment 0 core select - to be run in parallel */
BF_SET(stcREG2->STCGCR1, STC_GCR1_SEG0_CORE_PARLL, STC_GCR1_SEG0_CORE_SEL_START, STC_GCR1_SEG0_CORE_SEL_LENGTH);
BF_SET(stcREG2->STCGCR1, STC_GCR1_SEG0_CORE_PARLL, STC_GCR1_SEG0_CORE_SEL_START, STC_GCR1_SEG0_CORE_SEL_LENGTH);
/* Enable STC run */
stcREG2->STCGCR1 = STC_STCGCR1_STC_ENA;
stcREG2->STCGCR1 = STC_STCGCR1_STC_ENA;
/* Kick off the STC execution */
_gotoCPUIdle_();
