TMS570LS0714: We need more detail description for the STC (CPU Self-Test Controller) of TMS570

Hello Snaku,

STC is a controller which launches the LBIST selftest to the CPU.

When the selftest is launched to the CPU, some test patterns are stimulated to the CPU. The STC will then compare the test result (the signatures) of the test with the expected signatures stored in the STC's ROM. If a failure is detected then the STC will generate an error to the ESM module which eventually will assert the nRROR pin and notify the CPU via a NMI interrupt. When the selftest is launched to the CPU, it is the cpuSelfTest() at work.

The stcSelfCheck() is a selftest for the STC module itself just to make sure that it can properly generate error to the ESM if a fault is inserted to the compare logic. It doesn't test any registers.

Hi QJ,

Thanks for your reply, but I need to know what is done by the LBIST.

The datasheet only say it has 90.21% test coverage, but we don't know how you get this number, and what testing is done by the test patterns.

Could you provide pseudo code or assembly code to explain the function of the test patterns, like the SafeTI-60730 package for C2000 or MSP430.

About the stcSelfCheck() function, it sets the 'FAULT_INS' bit of the STCSCSCR register, and the reference manual says "Insert stuck-at-fault inside CPU so that STC signature compare will fail", and the comment of the source code is "stuck-at-0 fault insertion in CPU", so I need to know which part of CPU is affect by this action.

Regards,

Snaku

Hi QJ,

There is a E2E thread explain the stcSelfCheck() function, https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/251197.

But I still have no detail information for the LBIST, I need the description for the IEC60730-B CPU register test requirement.

Regards,

Snaku