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Original question:

TMS570LS3137: MIBSPI parity check

TMS570LS3137: Clarification on mibspi parity transmission

Someswararao malla
Intellectual 450 points
Part Number: TMS570LS3137

Hello Ti Experts,

I am using TMS570LS3137 micro controller and trying to transmit data over mibspi1 by connecting MISO and MOSI pins externally.

As per reference manual i enabled parity by updating Data format settings. As per the manual the parity bit should be transmitted/received at the end of the data word.

But i could not see the bit is being updating neither in the TXRAM nor in the RXRAM, the only place i could see the parity values being updated are in the PARITY RAM memory.

Please help me is there anything i am missing in my test or suggest me how to check the parity bit in the receive data.

Regards,

Somesh

  • 0
    TI__Guru**** 197036 points

    Hello,

    The parity value is not in TXRAM region or RXRAM region. The parity value are located at RAM_base address + 0x400 (parity RAM region).

    For MibSPI1, Buffer0:

    RX RAM address: 0xFF0E0200, Parity address is: 0xFF0E0600

  • 0 in reply to QJ Wang
    Intellectual 450 points

    Hi Wang,

    Thanks for the quick response, yes i am checking parity bits at 0xFF0E0400(TX) and 0xFF0E0600(RX). I suppose these values are calculated by the controller.

    I would like to verify the received parity bit along with the data which is supposed to be at the end of the data word, which i am not seeing it as received.

    Regards,

    Somesh

  • 0 in reply to Someswararao malla
    TI__Guru**** 197036 points

    Hi Somesh,

    I just did a test, and captured the waveform to show you the parity bit.

    1. Use SPI1 as master, SPI3 as slave. Even Parity is enabled. The charlen is 16 bits

    2. SPI1 transmits 2 16-bit words: 0x5FAB, and 0x5FBB. The parity for 0x5FAB is 1, and the parity for 0x5FBB is 0

    3. The waveform shows that 16-bit data is followed by 1-bit parity bit. 

    4. This parity bit is different from the parity value in TXRAM or RXRAM. In TXRAM and RXRAM, each byte of data has 1-bit parity, and 32-bit long of the data buffer (data length + status and control) has 4-bit parity.  

     

  • 0 in reply to QJ Wang
    Intellectual 450 points

    Thanks Wang,

    I tried the same and i have checked the transmitted data in the oscilloscope and could see the parity bit added at the end of the word.

    Is it possible for me to verify the same in the code by any means?

  • 0 in reply to Someswararao malla
    TI__Guru**** 197036 points

    No, the parity bit is not reflected in any register. If the received parity bit does not match with the locally calculated parity bit, the parity error flag (PARITYERR) is set.