CCS/LAUNCHXL2-570LC43: MIBSPI as slave problem

Tool/software: Code Composer Studio

I used HALCoGen to generate software code to communicate 2 LAUNCHXL2-570LC43 MCUs through MIBSPI3, the 2 MCUs transfer and receive an array of 128 word(16-bits).

In Slave code this condition "if(mibspiIsTransferComplete(mibspiREG3, 0)==1)" always false; despite of the 2 MCUs received all the data successfully.

I found this bug in the Errata (MIBSPI#136).

Transfer Complete Interrupt is not generated after the transfer is complete even though the transfer complete flag in register TGINTFLG (offset 0x84) is set.

The workaround is listed in the Errata (MIBSPI#136).

http://www.ti.com/lit/er/spnz232b/spnz232b.pdf

I followed the workaround mentioned there, I configured the unused TG1 to 0x80 (128) but the problem still exist.

here is the Slave configuration:

/** @file HL_mibspi.c 
* @brief MIBSPI Driver Implementation File
* @date 11-Dec-2018
* @version 04.07.01
*
*/

/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
* 
* 
* Redistribution and use in source and binary forms, with or without 
* modification, are permitted provided that the following conditions 
* are met:
*
* Redistributions of source code must retain the above copyright 
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the 
* documentation and/or other materials provided with the 
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/


/* USER CODE BEGIN (0) */
/* USER CODE END */

#include "HL_mibspi.h"
#include "HL_sys_vim.h"
/* USER CODE BEGIN (1) */
/* USER CODE END */

/* SourceId : MIBSPI_SourceId_001 */
/* DesignId : MIBSPI_DesignId_001 */
/* Requirements : HL_CONQ_MIBSPI_SR9 */
/** @fn void mibspiInit(void)
* @brief Initializes the MIBSPI Driver
*
* This function initializes the MIBSPI module.
*/
void mibspiInit(void)
{
uint32 i ;

/* USER CODE BEGIN (2) */
/* USER CODE END */




/** @b initialize @b MIBSPI3 */

/** bring MIBSPI out of reset */
mibspiREG3->GCR0 = 0U;
mibspiREG3->GCR0 = 1U;

/** enable MIBSPI3 multibuffered mode and enable buffer RAM */
mibspiREG3->MIBSPIE = (mibspiREG3->MIBSPIE & 0xFFFFFFFEU) | 1U;

/** MIBSPI3 master mode and clock configuration */
mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)0U << 1U) /* CLOKMOD */
| 0U); /* MASTER */

/** MIBSPI3 enable pin configuration */
mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */

/** - Delays */
mibspiREG3->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */
| (uint32)((uint32)0U << 16U) /* T2CDELAY */
| (uint32)((uint32)0U << 8U) /* T2EDELAY */
| (uint32)((uint32)0U << 0U); /* C2EDELAY */

/** - Data Format 0 */
mibspiREG3->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)0U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)74U << 8U) /* baudrate prescale */
| (uint32)((uint32)16U << 0U); /* data word length */

/** - Data Format 1 */
mibspiREG3->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)0U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)74U << 8U) /* baudrate prescale */
| (uint32)((uint32)16U << 0U); /* data word length */

/** - Data Format 2 */
mibspiREG3->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)0U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)74U << 8U) /* baudrate prescale */
| (uint32)((uint32)16U << 0U); /* data word length */

/** - Data Format 3 */
mibspiREG3->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */
| (uint32)((uint32)0U << 23U) /* parity Polarity */
| (uint32)((uint32)0U << 22U) /* parity enable */
| (uint32)((uint32)0U << 21U) /* wait on enable */
| (uint32)((uint32)0U << 20U) /* shift direction */
| (uint32)((uint32)0U << 17U) /* clock polarity */
| (uint32)((uint32)0U << 16U) /* clock phase */
| (uint32)((uint32)74U << 8U) /* baudrate prescale */
| (uint32)((uint32)16U << 0U); /* data word length */

/** - Default Chip Select */
mibspiREG3->DEF = (uint32)(0x02U);

/** - wait for buffer initialization complete before accessing MibSPI registers */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((mibspiREG3->FLG & 0x01000000U) != 0U)
{
} /* Wait */

/** enable MIBSPI RAM Parity */
mibspiREG3->PAR_ECC_CTRL = (mibspiREG3->PAR_ECC_CTRL & 0xFFFFFFF0U) | (0x0000000AU);

/** - initialize transfer groups */
mibspiREG3->TGCTRL[0U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)0U << 8U); /* start buffer */

mibspiREG3->TGCTRL[1U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)128U << 8U); /* start buffer */

mibspiREG3->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(128U+128U) << 8U); /* start buffer */

mibspiREG3->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(128U+128U+0U) << 8U); /* start buffer */

mibspiREG3->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(128U+128U+0U+0U) << 8U); /* start buffer */

mibspiREG3->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(128U+128U+0U+0U+0U) << 8U); /* start buffer */

mibspiREG3->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(128U+128U+0U+0U+0U+0U) << 8U); /* start buffer */

mibspiREG3->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */
| (uint32)((uint32)0U << 29U) /* pcurrent reset */
| (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */
| (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */
| (uint32)((uint32)(128U+128U+0U+0U+0U+0U+0U) << 8U); /* start buffer */


mibspiREG3->TGCTRL[8U] = (uint32)(128U+128U+0U+0U+0U+0U+0U+0U) << 8U;

mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(128U+128U+0U+0U+0U+0U+0U+0U)-1U) << 8U);

/** - initialize buffer ram */
{
i = 0U;

#if (128U > 0U)
{

#if (128U > 1U)

while (i < (128U-1U))
{
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)1U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)1U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */
i++;
}
#endif
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */


i++;
}
#endif

#if (128U > 0U)
{

#if (128U > 1U)

while (i < ((128U+128U)-1U))
{
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((128U+128U+0U)-1U))
{
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((128U+128U+0U+0U)-1U))
{
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((128U+128U+0U+0U+0U)-1U))
{
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((128U+128U+0U+0U+0U+0U)-1U))
{
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((128U+128U+0U+0U+0U+0U+0U)-1U))
{
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif

#if (0U > 0U)
{

#if (0U > 1U)

while (i < ((128U+128U+0U+0U+0U+0U+0U+0U)-1U))
{
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 11U) /* lock transmission */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */

i++;
}
#endif
mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
| (uint16)((uint16)0U << 12U) /* chip select hold */
| (uint16)((uint16)0U << 10U) /* enable WDELAY */
| (uint16)((uint16)0U << 8U) /* data format */
| ((uint16)(~((uint16)0x02U ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */
i++;
}
#endif
}

/** - set interrupt levels */
mibspiREG3->LVL = (uint32)((uint32)0U << 9U) /* TXINT */
| (uint32)((uint32)0U << 8U) /* RXINT */
| (uint32)((uint32)0U << 6U) /* OVRNINT */
| (uint32)((uint32)0U << 4U) /* BITERR */
| (uint32)((uint32)0U << 3U) /* DESYNC */
| (uint32)((uint32)0U << 2U) /* PARERR */
| (uint32)((uint32)0U << 1U) /* TIMEOUT */
| (uint32)((uint32)0U << 0U); /* DLENERR */

/** - clear any pending interrupts */
mibspiREG3->FLG |= 0xFFFFU;

/** - enable interrupts */
mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U)
| (uint32)((uint32)0U << 9U) /* TXINT */
| (uint32)((uint32)0U << 8U) /* RXINT */
| (uint32)((uint32)0U << 6U) /* OVRNINT */
| (uint32)((uint32)0U << 4U) /* BITERR */
| (uint32)((uint32)0U << 3U) /* DESYNC */
| (uint32)((uint32)0U << 2U) /* PARERR */
| (uint32)((uint32)0U << 1U) /* TIMEOUT */
| (uint32)((uint32)0U << 0U); /* DLENERR */

/** @b initialize @b MIBSPI3 @b Port */

/** - MIBSPI3 Port output values */
mibspiREG3->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)1U << 3U) /* SCS[3] */
| (uint32)((uint32)1U << 4U) /* SCS[4] */
| (uint32)((uint32)1U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)0U << 9U) /* CLK */
| (uint32)((uint32)0U << 10U) /* SIMO */
| (uint32)((uint32)0U << 11U); /* SOMI */

/** - MIBSPI3 Port direction */
mibspiREG3->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)0U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)1U << 3U) /* SCS[3] */
| (uint32)((uint32)1U << 4U) /* SCS[4] */
| (uint32)((uint32)1U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)0U << 9U) /* CLK */
| (uint32)((uint32)0U << 10U) /* SIMO */
| (uint32)((uint32)1U << 11U); /* SOMI */

/** - MIBSPI3 Port open drain enable */
mibspiREG3->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */
| (uint32)((uint32)0U << 1U) /* SCS[1] */
| (uint32)((uint32)0U << 2U) /* SCS[2] */
| (uint32)((uint32)0U << 3U) /* SCS[3] */
| (uint32)((uint32)0U << 4U) /* SCS[4] */
| (uint32)((uint32)0U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)0U << 9U) /* CLK */
| (uint32)((uint32)0U << 10U) /* SIMO */
| (uint32)((uint32)0U << 11U); /* SOMI */


/** - MIBSPI3 Port pullup / pulldown selection */
mibspiREG3->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)1U << 2U) /* SCS[2] */
| (uint32)((uint32)1U << 3U) /* SCS[3] */
| (uint32)((uint32)1U << 4U) /* SCS[4] */
| (uint32)((uint32)1U << 5U) /* SCS[5] */
| (uint32)((uint32)1U << 8U) /* ENA */
| (uint32)((uint32)1U << 9U) /* CLK */
| (uint32)((uint32)1U << 10U) /* SIMO */
| (uint32)((uint32)1U << 11U); /* SOMI */


/** - MIBSPI3 Port pullup / pulldown enable*/
mibspiREG3->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */
| (uint32)((uint32)0U << 1U) /* SCS[1] */
| (uint32)((uint32)0U << 2U) /* SCS[2] */
| (uint32)((uint32)0U << 3U) /* SCS[3] */
| (uint32)((uint32)0U << 4U) /* SCS[4] */
| (uint32)((uint32)0U << 5U) /* SCS[5] */
| (uint32)((uint32)0U << 8U) /* ENA */
| (uint32)((uint32)0U << 9U) /* CLK */
| (uint32)((uint32)0U << 10U) /* SIMO */
| (uint32)((uint32)0U << 11U); /* SOMI */


/* MIBSPI3 set all pins to functional */
mibspiREG3->PC0 = (uint32)((uint32)1U << 0U) /* SCS[0] */
| (uint32)((uint32)1U << 1U) /* SCS[1] */
| (uint32)((uint32)0U << 2U) /* SCS[2] */
| (uint32)((uint32)0U << 3U) /* SCS[3] */
| (uint32)((uint32)0U << 4U) /* SCS[4] */
| (uint32)((uint32)0U << 5U) /* SCS[5] */
| (uint32)((uint32)1U << 8U) /* ENA */
| (uint32)((uint32)1U << 9U) /* CLK */
| (uint32)((uint32)1U << 10U) /* SIMO */
| (uint32)((uint32)1U << 11U); /* SOMI */

/** - Finally start MIBSPI3 */
mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFEFFFFFFU) | 0x01000000U;




/* USER CODE BEGIN (3) */
/* USER CODE END */

}

Here is the code that sends and receiving the array:
void     main(void)
{
SPI_Init_Pins();
mibspiInit();
        mibspiSetData(mibspiREG3, 0, (uint16_t *) SPI_Module[SPI3].DataSentArray);
        if(SPI_Module[SPI3].MasterSlave!=SLAVE)
        {
            // Master puts CS to low
            mibspiREG3->PC3&= ~(0x00000002U);
        }
        mibspiTransfer(mibspiREG3, 0);

        while       (1)
        {

                    if(mibspiIsTransferComplete(mibspiREG3, 0)==1)
                    {
                        if(SPI_Module[SPI3].MasterSlave!=SLAVE)
                        {
                            // Master puts CS to high
                            mibspiREG3->PC3|= (0x00000002U);
                        }
                            mibspiGetData(mibspiREG3, 0, (uint16_t *) SPI_Module[SPI3].DataReceivedArray);
                            ArraytoStruct_Ver2(SPI_Module[SPI3].DataReceivedArray);
                            StructtoArray_Ver2(SPI_Module[SPI3].DataSentArray);
                            mibspiSetData(mibspiREG3, 0, (uint16_t *) SPI_Module[SPI3].DataSentArray);
                            if(SPI_Module[SPI3].MasterSlave!=SLAVE)
                            {
                                // Master puts CS to low
                                mibspiREG3->PC3&= ~(0x00000002U);
                            }
                            mibspiTransfer(mibspiREG3, 0);
                    }
        } // End of while loop
} // End of main()