Hello,
In our application the clock frequency configurations as as given below:
PLL Frequency 160 Mhz
External Oscillator 16 Mhz
During the PLL initialization we intend to check the PLL lock as per the workaround given in silicon errata SPNZ195G, design exception SSWF021#45. We used DCC module in single shot mode, to check the correctness of the PLL frequency. The DCC counter configurations are given below:
/** DCC1 Clock0 Counter Seed value configuration */
dccREG1->CNT0SEED = 138U;
/** DCC1 Clock0 Valid Counter Seed value configuration */
dccREG1->VALID0SEED = 10U;
/** DCC1 Clock1 Counter Seed value configuration */
dccREG1->CNT1SEED = 1480U;
After the register configurations, we enable the single shot mode and we wait for the DCC status register to become non-zero. Then we check whether the DONE bit in DCC status register is set to ensure the PLL frequency is set correctly. Please note, we used the algorithm from TI application note "Hercules PLL Advisory SSWF021#45 Workaround" "http://www.ti.com/lit/an/spna233b/spna233b.pdf"
We observed that there is an errata DCC#24 which states Single Shot Mode Count may be Incorrect. As mentioned above, in our application, we ensure the correctness of the PLL frequency by the DCC counter configurations ( Counter 0 to Counter 1 ratio = 1:10) and the DONE bit value in status register after triggering single shot mode and we don't use value in DCC Counter1 Value Register (DCCCNT1). Hence we believe issue DCC#24 is not applicable for us. Please confirm.
Thanks,
Sundaram
