Other Parts Discussed in Thread: TM4C1294NCPDT
Hi guys. I am doing a project with I2C, and I have been unable to trigger an interrupt based on how full the FIFO is. For instance, I want to trigger an interrupt when the Master TX hardware FIFO is half full. So I have set the proper bit to a value of 4 and unmasked bit number 8 in the I2CMIMR register. But no interrupt occurs. I CAN trigger an interrupt if I unmask bit number 10, for instance, when I empty the FIFO. SO interrupts are working.....but the way I understand it to work for the triggering must be wrong. Anyway, I am a FIFO half full kind of guy, so I am sure there is a solution. Data is also being sent just fine from the TX FIFO of I2C0 to the RX FIFO of I2C3. Everything is working how I want EXCEPT triggering an interrupt when I want to. Relevant code using built in API:
I2CMasterInitExpClk(I2C0_BASE, ui32SysClock, false);
I2CSlaveInit(I2C3_BASE, SLAVE_ADDRESS);
I2CMasterSlaveAddrSet(I2C0_BASE, SLAVE_ADDRESS, false);
uint32_t pui32DataTx[8] = {'F', 'I', 'F', 'O','L', 'O','V', 'E'};
I2CTxFIFOConfigSet(I2C0_BASE, (I2C_FIFO_CFG_TX_MASTER|I2C_FIFO_CFG_TX_TRIG_4));
I2CRxFIFOConfigSet(I2C3_BASE,(I2C_FIFO_CFG_RX_SLAVE|I2C_FIFO_CFG_RX_TRIG_4));
I2CSlaveFIFOEnable(I2C3_BASE,I2C_SLAVE_RX_FIFO_ENABLE);
IntEnable(INT_I2C0);
I2CMasterIntEnable(I2C0_BASE);
I2CMasterIntEnableEx(I2C0_BASE, I2C_SLAVE_INT_RX_FIFO_REQ);
IntEnable(INT_I2C3);
I2CSlaveIntEnable(I2C3_BASE);
I2CSlaveIntEnableEx(I2C3_BASE, I2C_SLAVE_INT_RX_FIFO_REQ);
I2CFIFODataPut(I2C0_BASE, pui32DataTx[0]);
I2CFIFODataPut(I2C0_BASE, pui32DataTx[1]);
I2CFIFODataPut(I2C0_BASE, pui32DataTx[2]);
I2CFIFODataPut(I2C0_BASE, pui32DataTx[3]); //*************************I want to trigger an interrupt here....when the TX FIFO is half full
I2CFIFODataPut(I2C0_BASE, pui32DataTx[4]);
I2CFIFODataPut(I2C0_BASE, pui32DataTx[5]);
I2CFIFODataPut(I2C0_BASE, pui32DataTx[6]);
I2CFIFODataPut(I2C0_BASE, pui32DataTx[7]);
I2CMasterBurstLengthSet(I2C0_BASE, 0x04);
I2CMasterControl(I2C0_BASE, I2C_MASTER_CMD_FIFO_BURST_SEND_START); //send the first 4 bytes to the RX FIFO
//******************************here the interrupt is triggered for I2C3 RX. This is working fine. the ISR just puts the data into a global data array and sets a flag to true
//wait for ISR to complete
while(!g_bIntFlag);
g_bIntFlag = false;
I2CMasterControl(I2C0_BASE, I2C_MASTER_CMD_FIFO_BURST_SEND_CONT); //send the last 4 bytes to the RX FIFO
//wait for ISR to complete
while(!g_bIntFlag);
g_bIntFlag = false;
I2CTxFIFOFlush(I2C0_BASE);
I2CRxFIFOFlush(I2C3_BASE);
Am I missing something important or is there some other problem with this feature??
Thanks!