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Original question:

TMS570* PCB Layout recommendations

TMS570LS3137: TMS570 Recommended Layout

Joey Han
Intellectual 575 points
Part Number: TMS570LS3137


Hello,

Has TI developed any additional guidance for PCB layout for the TMS570? The previous thread from 2017 indicated that the guidance available is limited to the devkit HDK essentially (https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/582423?TMS570-PCB-Layout-recommendations), have there been any more guidance defined?

Has anyone laid out a TMS570 on a PCB on one side only with positive results? We are curious as to the risk for laying out the bypass caps on primary side instead of secondary due to constraints we have on our current application. Would be helpful to know if anyone else has been successful in this kind of strange configuration.

Thanks,

Joey

  • 0
    TI__Guru**** 199106 points

    Hello Joey,

    We don't have PCB layout guidelines. Do you use 337-pin ZWT package or 144-pin PGE package? How many signals are used for your application? If all the signals are required, it is impossible to lay all the signals on one layer.

    Please be aware of that each digital signal has a return signal through the group trace. The signal and its return trace should run together and be of equal length. It is better to have a separate ground layer.  

    The CMOS circuits draw large currents at every transition, producing current spikes on the supply rails. The bypass or decoupling capacitors placed across the power pins and ground are used for such filtering. One capacitor on each power pin is recommended. The capacitor should be placed as close to the power pin as possible. For PGE package, the capacitors can be placed on top side or bottom side. For ZWT package, placing the capacitors on bottom side beneath the MCU is suggested.

  • 0 in reply to QJ Wang
    Intellectual 575 points

    Hi QJ, thanks for your feedback, apologies for the delayed response.

    We are using the 337 ZWT package. Currently using ~20-25 analog ports, ~15 GPIO, some comm peripherals, ~16 HET inputs.. call it ~75 total signals or so.

    We will plan to have dedicated power and ground layers. The bypass/decoupling caps would be as close to physically possible around the perimeter of the footprint to minimize distance as best we can on the primary side. Good to know regarding the recommendation for matching digital signal and return trace length. 

    If we are able to place a minimum of one cap per power pin as close as possible (on primary/top side), and accommodate your other suggestions, do you believe that this configuration would incur significantly more risk than opening up the space below the BGA for a more traditional layout scheme in line with your general recommendation?

    Thanks,

    Joey

  • 0 in reply to Joey Han
    Intellectual 575 points

    Hi QJ, is there a way for us to share a PM or email on this topic? I have a top side layout concept that reflects your recommendations as provided and would like to share some additional dialogue if possible without posting it to this forum.

    Thanks,

    Joey

  • 0 in reply to Joey Han
    TI__Guru**** 199106 points

    Hi Joey,

    It sounds like a good idea, but I haven't tried this way before. 

  • 0 in reply to QJ Wang
    TI__Guru**** 199106 points

    close this thread, and discuss offline