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Original question:

Ambiguous NOTE regarding VCLK, VCLK2 relationship requirement

TMS570LS3137: VCLK and VCLK2 ratio note

Kevin Uker
Prodigy 50 points
Part Number: TMS570LS3137


Hello,

In the technical reference manual (SPNU499C) section 2.5.1.44 the following note is found:

NOTE: VCLK and VCLK2 clock ratio restrictions. The VCLK2 frequency must always be greater than or equal to the VCLK frequency. The VCLK2 frequency must be an integer multiple of the VCLK frequency. In addition, the VCLK and VCLK2 clock ratios must not be changed simultaneously. When increasing the frequency (decreasing the divider), first change the VCLK2R field and then change the VCLKR field. When reducing the frequency (increasing the divider), first change the VCLKR field and then change the VCLK2R field. You should do a read-back between the two writes. This assures that there are enough clock cycles between the two writes.

Question: What is the potential effect of violating the VCLK and VCLK2 clock ratio restrictions?

Thanks 

  • 0
    TI__Mastermind 49120 points

    Hello,

    VCLK2 domain is only used by the high-end-timer (N2HET) and the HTU modules. Violating the VCLK2/VCLK ratio requirement, or the sequence for updating these clock ratios causes issues with the HET operation.

    In case VCLK2 frequency is not an integer multiple of VCLK2 frequency, the interface signals to/from the N2HET will not work correctly. These are DMA requests, interrupt requests, etc.

    In case VCLK2R and VCLKR are updated with the same write instruction this ratio update may not happen at all, leaving the clocks in the previously configured states.

  • 0 in reply to Sunil Oak
    Prodigy 50 points

    Thank you, that information is very helpful. 

    I have a follow on question.

    Specifically if there is any effect if the VCLK2 frequency being less than the VCLK frequency for a small amount of time,( i.e. 4 CPU clocks it takes to write the divider)?

    I doubt there would be as we would not be getting data from the HET yet.

    Thank you.

  • 0 in reply to Kevin Uker
    TI__Mastermind 49120 points

    It takes several more cycles for the writes to complete. These are posted writes from a CPU perspective, which is why it appears to only take 4 CPU clocks between the writes. Do you also a read back from the register between the two writes? Typically byte-writes are used for setting up these divide ratios.

    That said, there should be no effects as long as the HETx or HTU are not enabled at the time of setting up these clock ratios. I will confirm with someone on the design team and get back to you.

    Thanks.

  • 0 in reply to Sunil Oak
    Prodigy 50 points

    Thank you Sunil for your help.  Much appreciated.

    Kevin