Hello Stephan,

The test procedure for "Redundant Address Decode Self Test" is listed in 8.2.6:

1. Write 0x0 or any value to DIAG_DATA_VECTOR_H, DIAG_DATA_VECTOR_L

2. write the ECC value (for example 0x0c) of data vector in stel #1

3. In RAMTEST, write TEST_ENABLE field with Ah and TEST_MODE field with the choice of inequality or equality testing for redundant address decoding and SECDED multifunction diagnostics.

4. In RAMTEST, write TRIGGER bit.

5. check error status register (RAMERRSTATUS), and ESM Group2 status register.

SW test of SRAM Wrapper Addr Decode and ECC:

My understanding is to directly access the ECC bits in the memory map to insert single bit and dual bit errors.

You can use the API defined in SafetyLibrary for ECC error injection test:

SL_SelfTest_SRAM()

Dear QJ,

Thank you for your explanations. Now i understand what each of the tests RAM12, RAM13 and RAM17 focuses on.

The RAM17 and its description in section 8.2.6 of the TRM spnu563a is still a mystery for me.
There's a figure showing some aspects of the diagnostics of the redundant address decode RAM5 within the (L2RAMW):

Do you know whether there is a more comprehensive drawing showing the registers DIAG_DATA_VECTOR_H, DIAG_DATA_VECTOR_L, DIAG_ECC too?

Thank you inadvance!

Stephan

Hi Stephan,

DIAG_DATA_VECTOR_H, DIAG_DATA_VECTOR_L, DIAG_ECC are used for SECDED multifunction diagnostics. I don't have a similar diagram as one you posted.

Hi, QJ,

Thank you for hint regarding SafeTILib.

We're currently investigating how to populate DIAG_DATA_VECTOR_H, DIAG_DATA_VECTOR_L, DIAG_ECC in detail.
If we are succsessful we'll post a more comprehensive diagram showing how DIAG_DATA_VECTOR_H, DIAG_DATA_VECTOR_L, DIAG_ECC are working in detail.

Stephan