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Original question:

TMS570LC4357: Differences between RAM12 "Software Test of SRAM Wrapper Address Decode and ECC" and RAM17 "Redundant Address...

TMS570LC4357: Data Abort exception while writing to Diagnostic ECC Vector Register[DIAG_ECC]

Kalyan Vagvala61
Expert 1075 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hello,

I am trying to implement SRAM ECC test on TMS570LC4357 microcontroller and getting Data abort exception while writing to DIAG_ECC register. 

This data abort exception is happening when commenting out the "_mpuInit_();" function call in HL_sys_startup.c file.

can you please help me what could be the issue in this case?

SRAM ECC memory content in CCS memory browser shows as "?????" with _mpuInit_();. without _mpuInit_(); SRAM ECC memory contents were "0C0C0C0C".

Does that mean any issue with my MPU configuration?

Thanks,

Kalyan

  • 0
    TI__Guru**** 197356 points

    Hello, 

    When the MPU is disabled, no access permission checks are performed, and memory attributes are assigned according to the default memory map. The RAM ECC memory range is configured as no-shared device mode.

    In the HALCOGen default MPU settings, the RAM ECC range is not defined and the background region is not enabled. If MPU is enabled, all accesses for an address that is not mapped to a region in the MPU generate a background fault. We can avoid this by enabling the background region in HALCOGen. This will configure the region 1 as a 4GB background region. In this way, if the address does not fall into any of the defined regions, the attributes and access permissions you specified for region 1 control the access.

  • 0 in reply to QJ Wang
    Expert 1075 points

    Thanks Wang for your prompt response.

    Below question is not related to MPU but related to RAM ECC. I am trying below procedure for testing RAM ECC Single BIT error:

    1. Disable ECC detection in CPU.

    2. Disable ECC detection in L2RAMW module.

    3. Corrupt ECC memory by one bit after enabling writes to ECC memory.

    4. Enable ECC detection in CPU.

    5. Enable ECC detection in L2RAMW module.

    6. Disable writes to ECC memory.

    7. Read corrupted RAM memory location.

    Expecting ESM fault (L2RAMW - correctable error Group1 Bit 26). 

    When i tested above procedure i am not getting any ESM error. Can you please suggest if the above procedure will work?

    Below few related question:

    1. Below statement is from TRM. Does this mean that L2RAM ECC detection is enabled upon reset?

    "The SECDED logic inside the CPU is permanently enabled for the AXI-M and AXI-S
    interfaces."

    2. Does EPC module needs to be configured to report errors detected in CPU to ESM module?

    Can you please provide your inputs in this context.

    Thanks,

    Kalyan

  • 0 in reply to Kalyan Vagvala61
    TI__Guru**** 197356 points

    Hello Kalyan,

    For L2RAM ECC selftest, Please follow the procedure described in 8.2.6 of TRM:

    1. Clear error status register: RAMERRSTATUS

    2. Write test vectors DIAG_DATA_VECTOR_H, DIAG_DATA_VECTOR_L, DIAG_ECC

    3. In RAMTEST, write TEST_ENABLE field with Ah and TEST_MODE field with the choice of inequality or equality testing

    4. In RAMTEST, write TRIGGER bit. Remember the trigger can only be enabled when TEST_ENABLE is equal to Ah and  RAMERRSTATUS [22, 21, 20, 19, 12, 11, 10, 4] bits are zero.

    5. The ESM group2 will be set if there is error

    The ECC is enabled by default, and can not be disabled. The EPC should be initialized before using it: to clear the entry for CAM usage.